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Research digest · Friday, August 14, 2026 研究摘要 · 2026年8月14日 星期五

Integration Moves from Devices to Full Systems 集成从单器件走向完整系统

This week's strongest work connects materials and devices to manufacturable stacks, network behavior, and system-level performance. Wafer-scale oxide integration, photonic compute, MoE switching, and tunable quantum structures all show that interfaces now determine whether a promising device becomes useful hardware. 本周最值得关注的研究把材料与器件进一步连接到可制造堆叠、网络行为和系统级性能。晶圆级氧化物集成、光子计算、MoE交换与可调量子结构共同表明，接口设计正决定一种潜力器件能否成为实用硬件。

Look-back window: 7 days · 8 paper(s) 回溯窗口: 7天 · 8篇

Devices & Process 器件与工艺

200 mm Wafer-Scale Monolithic 3D Integration of ALD Oxide Semiconductors 200 mm晶圆级ALD氧化物半导体单片3D集成

C. Niu, L. Long, L. Zheng, et al.

arXiv:2608.09508 · 2026-08-10

The team fabricated more than 100,000 ALD InOx devices across three monolithically integrated tiers on 200 mm silicon, including ferroelectric and enhancement- and depletion-mode FETs. Threshold-voltage variation reaches 0.04 V standard deviation, electron mobility reaches 91.6 cm²/V·s, and cross-tier circuits operate; a modeled four-tier CIM accelerator delivers 1.4×–2.9× speedup over 2D baselines. The wafer-scale device data are the key result, while the accelerator comparison remains design-level evidence and the preprint does not yet establish production yield or long-term reliability. 研究团队在200 mm硅片上单片集成三层、超过100,000个ALD InOx器件，包括铁电FET以及增强型和耗尽型FET。器件阈值电压标准差低至0.04 V，电子迁移率最高91.6 cm²/V·s，跨层电路可以工作；基于该工艺设计的四层CIM加速器相对2D基线获得1.4×–2.9×加速。晶圆级器件数据是核心成果，但加速器比较仍属于设计层证据，预印本也尚未证明量产良率和长期可靠性。

Telecom Light Sources from MoS₂/WSe₂ Moiré Superlattices on Silicon Photonics 硅光平台上的MoS₂/WSe₂莫尔超晶格通信波段光源

X. Huang, H. Fang, S. Kadkhodazadeh, et al.

Science Advances · 2026-08-07

MoS₂/WSe₂ moiré superlattices coupled to a silicon-photonic nanobeam cavity produce a waveguide-integrated light source in the telecom O-band at room temperature. The device reports near-unity interference visibility and a coherence length of about 3.8 mm, substantially extending the coherence demonstrated by earlier 2D-material emitters. Stable ambient operation is encouraging for integration, although the paper does not by itself establish electrical pumping or foundry-scale manufacturing. MoS₂/WSe₂莫尔超晶格与硅光纳米梁腔耦合，在室温下实现了通信O波段的波导集成光源。器件报告接近1的干涉可见度和约3.8 mm相干长度，明显超过此前二维材料发光器件的相干表现。其环境稳定性有利于集成，但论文尚不能证明电泵浦能力或晶圆代工规模的制造可行性。

Circuits, Architecture & Reliability 电路、架构与可靠性

SLAC Exposes CPU-to-GPU Cache Side Channels on Apple Silicon SLAC揭示Apple Silicon上的CPU到GPU缓存侧信道

T. Xu, S. K. Roy, R. Ding, et al.

arXiv:2608.09075 · 2026-08-10

SLAC shows that an unprivileged CPU process can observe cache-set footprints left by GPU memory accesses in the shared system-level cache of Apple Silicon. After reverse-engineering the M1 cache indexing, the authors build a Prime+Probe-style CPU-to-GPU channel; GPU-assisted priming increases covert-channel throughput by 6.4×. The result identifies a fine-grained cross-domain attack surface, but it is a preprint demonstrated on M1-class behavior and should not yet be generalized to every Apple generation. SLAC发现，在Apple Silicon共享的系统级缓存中，非特权CPU进程可以观察GPU访存留下的缓存组足迹。团队逆向分析M1缓存索引后，构建了Prime+Probe式CPU到GPU侧信道；借助GPU进行预填充后，隐蔽信道吞吐率提高6.4×。该结果揭示了细粒度跨域攻击面，但目前仍是基于M1行为的预印本，不宜直接推广到所有Apple芯片世代。

Giant Backward Brillouin Interaction in Foundry-Accessible InP Photonics 可晶圆代工InP光子平台中的巨型后向布里渊相互作用

R. te Morsche, L. Puts, W. Yao, et al.

arXiv:2608.07241 · 2026-08-07

The work reports the first measured backward stimulated Brillouin scattering in generic InP waveguides, with gain coefficients reaching 737 ± 54 W⁻¹m⁻¹. Achieving that interaction in a mature, foundry-accessible platform could add narrowband filtering, delay, and microwave-photonic functions without a bespoke material stack. The result is a preprint and the reported gain comes from a specific waveguide and acoustic-mode configuration, so circuit-scale loss and reproducibility remain the practical tests. 该研究首次在通用InP波导中测得后向受激布里渊散射，增益系数最高达到737 ± 54 W⁻¹m⁻¹。在成熟、可晶圆代工的平台上获得这一相互作用，有望无需定制材料堆叠即可加入窄带滤波、延迟和微波光子功能。该结果仍是预印本，且高增益来自特定波导与声学模式配置，电路级损耗和重复性仍需验证。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

A Subvolt Dual-Mode Silicon Microring for Analog Optical Computing 面向模拟光计算的亚伏双模式硅微环

S. Biswas, S. M. Bari, A. X. Wang

ACS Photonics · 2026-08-10

A MOSCAP silicon microring gated by a high-mobility transparent conductive oxide reaches 175 pm/V tuning efficiency, VπL of 0.09 V·cm, more than 6 dB extinction at 0.5 V, and 13.5 fJ/bit. Accumulation and depletion biasing let the same device encode 5- to 6-bit analog weights or provide a nonlinear optical response, reducing the need for separate photonic elements. These are strong measured device metrics, but scaling one ring into a calibrated multi-ring computing system remains the decisive systems challenge. 一种由高迁移率透明导电氧化物栅控的MOSCAP硅微环实现175 pm/V调谐效率、0.09 V·cm的VπL、0.5 V驱动下超过6 dB消光比，以及13.5 fJ/bit能效。通过积累区和耗尽区偏置，同一器件既可编码5至6 bit模拟权重，也可提供非线性光响应，从而减少独立光子器件数量。器件实测指标很强，但从单个微环扩展到可校准的多微环计算系统仍是决定性的系统挑战。

Polarity-Addressed Reset Stabilizes SiNW-FET Reservoir Computing 极性寻址复位稳定SiNW-FET储备池计算

L. Yan, Y. Zhang, M. Wei, et al.

Advanced Functional Materials · 2026-08-07

Trap-engineered Schottky silicon-nanowire FETs use source-drain polarity reversal as a device-native reset that clears accumulated state during continuous event-stream inference. The authors integrate roughly 20 nm nanowires into an addressable 4×4 top-gated array and trigger sparse resets from online drift statistics, addressing a failure mode hidden by segmented benchmarks. The measured array makes the reliability problem concrete, though its small scale and gesture-recognition workload leave larger reservoirs and broader tasks untested. 陷阱工程Schottky硅纳米线FET利用源漏极性反转实现器件原生复位，在连续事件流推理中清除累积状态。研究团队把直径约20 nm的纳米线集成为可寻址4×4顶栅阵列，并根据在线漂移统计稀疏触发复位，解决分段基准测试会掩盖的失效模式。实测阵列把可靠性问题具体化，但规模较小且仅使用手势识别任务，更大储备池和更广泛工作负载仍未验证。

AI Research for Hardware 面向硬件的AI研究

HyNA Uses Hybrid Switch Silicon to Tame MoE Tail Latency HyNA以混合交换芯片抑制MoE尾延迟

Y. Liu, T. Liu, H. Yao

ACM SIGCOMM 2026 · 2026-08-11

HyNA combines wire-speed reconfigurable match tables with embedded RISC-V cores so sparse, bursty MoE aggregation—including collisions and overflow handling—stays inside the switch ASIC. The design removes dedicated parameter-server nodes and is evaluated with a 100 Gbps FPGA prototype plus 7 nm ASIC synthesis, turning host fallback round trips into deterministic on-chip handling. The systems idea directly targets MoE communication tails, but the final performance and power claims still mix prototype measurements with synthesized rather than taped-out silicon. HyNA把线速可重构匹配表与嵌入式RISC-V核心结合，使稀疏、突发的MoE聚合流量连同冲突和溢出处理都留在交换ASIC内部。该设计取消专用参数服务器节点，并通过100 Gbps FPGA原型和7 nm ASIC综合评估，把主机回退的网络往返变为确定性的片上处理。其系统思路直接针对MoE通信尾延迟，但最终性能与功耗结论仍混合了原型实测和综合结果，而非流片芯片数据。

Quantum & Nonlinear Photonics 量子与非线性光子学

Tunable Bound States Reshape Four-Wave Mixing in SiN Microresonators 可调连续域束缚态重塑SiN微谐振器四波混频

E. C. Lima, M. Clementi, A. Viola, et al.

arXiv:2608.07426 · 2026-08-07

An electrically tunable Friedrich-Wintgen bound state in the continuum reaches Q above 10⁶ in coupled silicon-nitride microresonators and can be populated through spontaneous four-wave mixing despite being dark to linear excitation. Placing the idler at the bound-state condition increases parametric gain by 12 dB and lowers the oscillation threshold by 1.6 dB, while changing photon-pair correlations and coherence. The experiment points to reconfigurable quantum and nonlinear sources, but it remains a preprint and does not yet address packaging, control overhead, or device-to-device variation. 耦合SiN微谐振器中的电可调Friedrich-Wintgen连续域束缚态实现超过10⁶的Q值；尽管线性激励无法直接访问，该模式仍可通过自发四波混频被占据。把闲频模式调到束缚态条件后，参量增益提高12 dB，振荡阈值降低1.6 dB，同时改变光子对的关联与相干性。该实验为可重构量子和非线性光源提供路径，但目前仍是预印本，尚未处理封装、控制开销和器件间差异。

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