Memory Traffic Becomes the Optimization Target 内存流量成为优化主目标

This week's strongest systems papers attack the hidden cost of moving and retaining state: draft-model KV reads, cache eviction, low-bit activation transforms, and adapter capacity. The recurring lesson is that efficiency claims need attribution and bounded working sets, not just smaller nominal models. 本周最值得关注的系统论文集中处理状态搬运与保留的隐性成本：草稿模型的KV读取、缓存淘汰、低比特激活变换以及适配器容量。反复出现的结论是，效率不仅取决于名义上的模型缩小，还需要可归因的误差和有界工作集。

Look-back window: 7 days · 7 paper(s) 回溯窗口: 7天 · 7篇

AI Accelerators & Compute-in-Memory AI加速器与存算一体

Windowed-MTP Removes Full-Context Draft KV Reads Windowed-MTP消除草稿模型的全上下文KV读取

Alagappan Valliappan

arXiv:2607.21535 · 2026-07-23T17:21:44Z

Windowed-MTP applies a sliding attention window and sink only to the multi-token-prediction draft head, preventing draft cost from growing with a million-token KV cache. Full-attention verification remains unchanged, so the method can alter proposed tokens but not the target model's accepted output. It is a training-free systems optimization; the preprint still needs independent evaluation across model families and serving stacks. Windowed-MTP仅在多Token预测草稿头中应用滑动注意力窗口和attention sink，避免草稿成本随百万Token KV缓存线性增长。全注意力验证保持不变，因此该方法可以改变候选Token，却不会改变目标模型最终接受的输出。这是一项免训练的系统优化，但仍需在不同模型家族和推理栈上进行独立评估。

KroQuant Uses Kronecker Blocks for W4A4 Diffusion Transformers KroQuant以Kronecker块实现扩散Transformer的W4A4量化

Yann Bouquet, Alireza Khodamoradi, Kristof Denolf, et al.

arXiv:2607.21446 · 2026-07-23T15:52:20Z

KroQuant introduces learned Kronecker-structured invertible transforms on 32-element activation blocks to make W4A4 post-training quantization practical for diffusion transformers. The block-local construction targets the online transform cost that recurs at every denoising step and stores less than half as many parameters as per-channel scaling. The preprint's value will depend on whether image quality and latency gains persist on current accelerator kernels rather than only in calibration experiments. KroQuant在32元素激活块上引入可学习的Kronecker结构可逆变换，以提升扩散Transformer进行W4A4训练后量化的可行性。其块内结构针对每个去噪步骤都会重复出现的在线变换成本，参数存储量不到逐通道缩放的一半。该预印本的价值取决于图像质量与延迟收益能否在现有加速器kernel上保持，而不只是在校准实验中成立。

AI Research for Hardware 面向硬件的AI研究

Randomized KV Eviction Produces Serving-Time Error Certificates 随机化KV淘汰可生成推理时误差证书

Peng Xie

arXiv:2607.21475 · 2026-07-23T16:16:59Z

The paper proves that deterministic top-k KV-cache eviction cannot consistently estimate the attention error caused by discarded values, then restores identifiability with Poisson sampling and a Hájek correction. Its certificate reached 0.97 empirical coverage and distinguished cache-induced from inherent failures at AUC 0.73-0.75, but it did not improve failure prediction or certificate-gated budget escalation. The result is useful precisely because it narrows the claim: randomization supports attribution, not a universal serving-quality predictor. 论文证明，确定性的top-k KV缓存淘汰无法一致估计丢弃value造成的注意力误差，随后通过Poisson采样和Hájek校正恢复可识别性。误差证书取得0.97的经验覆盖率，并以0.73至0.75的AUC区分缓存诱发故障与固有故障，但未改善故障预测或证书驱动的预算升级。该结果的价值正在于收窄了主张：随机化有助于误差归因，而不是提供通用的推理质量预测器。

Early Activations Weakly Predict Reasoning Non-Convergence 早期激活可弱预测推理不收敛

Renuka Oladri, Niveda Jawahar, Abdirisak Mohamed

arXiv:2607.21433 · 2026-07-23T15:37:04Z

On DeepSeek-R1-Distill-Qwen-7B, converged chains scored 90.3% on AIME 1983-2024 while budget-exhausted chains scored 6.6%, with only 62.0% of generations converging. A linear probe at layer 20 and token 150 achieved AUC 0.608, suggesting a modest early signal that could support stopping policies. The permutation result was p=0.063, so the evidence does not yet clear conventional significance thresholds and should not be treated as a production-ready predictor. 在DeepSeek-R1-Distill-Qwen-7B上，收敛推理链在AIME 1983-2024上的准确率为90.3%，耗尽Token预算的推理链仅为6.6%，总体收敛率为62.0%。位于第20层、第150个Token的线性探针取得0.608 AUC，说明存在可用于提前停止策略的弱信号。置换检验结果为p=0.063，尚未达到常规显著性阈值，因此不能把它视为可直接用于生产的预测器。

Measuring How Many Bits a LoRA Adapter Can Store 量化LoRA适配器能够存储多少比特

Kaizhen Tan, Heqing Du, Yang Feng

arXiv:2607.21351 · 2026-07-23T14:16:43Z

A compression-based analysis finds that LoRA adapters store only a few bits per trainable parameter, and that placement matters more than raw parameter count. Moving the same budget from attention into the MLP nearly doubled capacity, while removing structure from the frozen base largely erased it; measured privacy leakage tracked stored bits more closely than nominal adapter size. The study reframes adapter design and risk around effective information capacity, though its conclusions still depend on the tested Qwen2.5 fine-tuning setups. 一项基于压缩的分析发现，LoRA适配器每个可训练参数只存储少量比特，而且参数位置比名义数量更重要。把相同预算从attention移到MLP后容量接近翻倍，而去除冻结基座的结构后容量几乎消失；测得的隐私泄露也更紧密地跟随实际写入比特，而非适配器名义大小。该研究把适配器设计与风险重新聚焦于有效信息容量，但结论仍取决于所测试的Qwen2.5微调设置。

Quantum Computing 量子计算

Deeper Parameterized Quantum Circuits Show Double Descent 更深参数化量子电路呈现双下降现象

Marie Kempkes, Elies Gil-Fuster, Carlos Bravo-Prieto, et al.

arXiv:2607.21409 · 2026-07-23T15:11:31Z

The authors show analytically and numerically that gradient-trained parameterized quantum circuits can improve out-of-sample performance as model size grows, exhibiting double descent rather than monotonically worsening generalization. Experiments on re-uploading circuits across several datasets support the predicted scaling behavior. The evidence is numerical rather than a hardware demonstration, so noise, trainability, and device depth remain separate obstacles to practical quantum machine learning. 作者通过解析推导和数值实验表明，采用梯度训练的参数化量子电路可随模型规模扩大而改善样本外表现，呈现双下降现象，而不是泛化能力单调恶化。在多个数据集上的re-uploading电路实验支持这一预测的扩展规律。不过证据来自数值实验而非硬件演示，噪声、可训练性和器件深度仍是实用量子机器学习的独立障碍。

EDA & Design Automation EDA与设计自动化

A Three-Stage Optimizer for Fixed-Outline Chip Floorplanning 面向固定轮廓芯片布局的三阶段优化器

Yilihamujiang Yimamu, Guillem Pastor-Rué, Jordi Cortadella

arXiv:2607.21408 · 2026-07-23T15:10:41Z

This floorplanning framework combines quadratic placement, Adam-based non-convex global optimization, and convex legalization based on horizontal and vertical constraint graphs. On MCNC, GSRC, and HB+ benchmarks, it reduced average half-perimeter wirelength by at least 1% and 5% versus the compared state-of-the-art floorplanners. The gains are benchmark results rather than tape-out evidence, so downstream timing, routability, and runtime behavior remain to be demonstrated. 该布局规划框架依次结合二次布局、基于Adam的非凸全局优化，以及依托水平和垂直约束图的凸合法化。在MCNC、GSRC和HB+基准上，其平均半周长线长相较所对比的先进布局器至少降低1%和5%。这些收益来自基准测试而非流片验证，后续时序、可布线性和运行时间表现仍有待证明。