Memory Goes Magnetic; MoE Serving Splits Apart 存储走向磁性，MoE服务架构走向分裂

This week's literature centers on two threads: MRAM-and-magnetic device candidates re-emerging as the cleanest path to in-memory CNNs, and the AFD / disaggregation movement at the systems level — both pointing at the same diagnosis that current monolithic GPU pods are mismatched to MoE-shaped workloads. 本周文献集中于两条主线：MRAM与磁性器件作为存内CNN最干净路径重新登场；以及系统层面的AFD／解耦运动——两者都指向同一诊断：当前单体GPU pod架构与MoE形状的负载并不匹配。

Look-back window: 7 days · 9 paper(s) 回溯窗口: 7天 · 9篇

Devices & 3D-IC 器件与3D-IC

Reconfigurable multistate MRAM synapses with vortex STNO neurons for scalable in-memory CNNs 面向可扩展存内CNN的多态可重构MRAM突触与涡旋STNO神经元 preprintMRAMneuromorphic

co-authors not extracted

spintronics research consortium

arXiv:2605.29942 · 2026-05-28

Proposes a unified MRAM + spin-torque nano-oscillator (STNO) architecture where MTJ multistate cells serve as synaptic weights and vortex STNOs serve as oscillator-neurons — all on a CMOS-compatible substrate. The interesting move is folding synapse and neuron onto the same device family rather than the usual MRAM-only weight-store + CMOS neuron pattern; in their simulated CNN deployments this cuts neuron-side area and energy dramatically. Still simulation, not measured silicon at scale, but it points at the architectural template for a credible MRAM-native edge accelerator. 提出统一的MRAM + 自旋力矩纳米振荡器（STNO）架构：MTJ多态单元作为突触权重，涡旋STNO作为振荡器神经元，全部位于CMOS兼容衬底。亮点在于把突触和神经元折叠到同一器件家族，而非常见的「MRAM只做权重存储+CMOS做神经元」模式；在模拟的CNN部署中，神经元侧的面积与能耗均大幅下降。仍属仿真层级而非规模化实测硅片，但已为可信的MRAM原生边缘加速器提供了清晰架构模板。

Design-oriented modeling of TSV substrate-noise coupling to ring VCOs 面向设计的TSV衬底噪声向环形VCO耦合建模 preprint3D-ICmixed-signal

co-authors not extracted

academic team

arXiv:2605.29867 · 2026-05-28

Derives a closed-form three-port RLGC macromodel for TSV-induced substrate-noise coupling into ring VCOs in mixed-signal 3D-IC stacks — validated on a three-stage ring VCO in 22nm FD-SOI. The contribution is making TSV noise tractable for analog-block layout at design time, instead of requiring full EM extraction after the fact. Practical relevance: as chiplet RF/analog blocks get placed adjacent to TSV-dense digital tiles, the spectral purity of PLLs and clock distribution depends on whether designers have a tool like this in their flow. 推导出TSV在混合信号3D-IC堆叠中向环形VCO产生衬底噪声耦合的闭式三端RLGC宏模型，并在22 nm FD-SOI的三级环形VCO上得到验证。贡献在于：在设计阶段就能让TSV噪声变得可处理，而无需事后做完整电磁场提取。实际意义：随着chiplet中的射频/模拟模块越来越多地与TSV密集的数字单元相邻放置，PLL与时钟分发的频谱纯度，将取决于设计者流程中是否有此类工具。

In-Memory & Memristor 存内计算与忆阻器

PRISM: processing-in-memory sparse MTTKRP for tensor decomposition acceleration PRISM：面向张量分解加速的存内稀疏MTTKRP preprintPIMtensor decomposition

co-authors not extracted

academic team

arXiv:2605.29728 · 2026-05-28

Tensor decomposition (CP-ALS) is a sneaky-important workload for recommendation systems, scientific computing, and certain ML feature-extraction paths — and the inner loop (Sparse MTTKRP) is bandwidth-bound in ways PIM is meant to address. PRISM is a co-designed PIM datapath that handles the irregular sparse-access patterns this kernel demands, with measured speedups vs. host-CPU baselines. Worth tracking because tensor decomposition is one of the rare AI-adjacent workloads where PIM advantage isn't theoretical — the memory-bandwidth gap is structural. 张量分解（CP-ALS）是推荐系统、科学计算与某些ML特征提取路径中悄然重要的负载——而其内层循环（Sparse MTTKRP）的带宽受限模式，正是PIM被设计来解决的。PRISM是面向该核所需的不规则稀疏访问模式联合设计的PIM数据通路，相对主机CPU基线给出实测加速。值得关注的原因：张量分解是少数AI相邻负载中、PIM优势并非理论而是结构性的领域——其内存带宽缺口是结构性的。

Uncertainty-triggered wake-up: memristor front-end for energy-efficient edge AI 不确定性触发唤醒：面向高能效边缘AI的忆阻器前端 preprintmemristoredge AI

co-authors not extracted

academic team

arXiv:2605.29533 · 2026-05-28

Couples a fabricated memristor Bayesian machine — operating as an always-on, ultra-low-power probabilistic screener — to a programmable CPU running a higher-accuracy software neural net that only fires when the memristor front-end's uncertainty crosses a threshold. The argument is structural: memristor variability and integration friction don't matter at the screening layer; they only matter if you make the memristor the final decision-maker. This is a more honest device-system pairing than the usual memristor-replaces-everything pitch. 把已经流片的忆阻器贝叶斯机器（作为常驻开机、超低功耗的概率筛选器）与运行更高精度软件神经网络的可编程CPU耦合：仅当忆阻器前端的不确定性越过阈值时才唤醒CPU。论点是结构性的：忆阻器的器件波动与集成摩擦在筛选层并不重要；只有当你让忆阻器做最终决策时，才变得致命。这是比常见的「忆阻器取代一切」更诚实的器件-系统配对方式。

MoE Serving & Networks MoE服务与网络

How far can disaggregation go? Attention-FFN disaggregation for efficient MoE LLM serving 解耦能走多远？面向高效MoE LLM服务的注意力-FFN解耦 preprintMoEdisaggregation

co-authors not extracted

academic team

arXiv:2605.28302 · 2026-05-27

Maps the design space of Attention-FFN Disaggregation (AFD) for MoE serving — placing memory-bound attention work and compute-intensive expert-FFN work on physically distinct resource pools, with the MoE dispatch/combine pattern as the communication layer between them. The contribution isn't claiming AFD wins everywhere; it's a rigorous exploration of when AFD beats the simpler prefill-decode disaggregation and when it doesn't. Practical relevance: vendors building MoE inference appliances (Cerebras, Groq, FuriosaAI) all need this design-space analysis before committing silicon partitions. 对MoE服务下「注意力-FFN解耦（AFD）」的设计空间进行刻画：把内存受限的注意力工作与计算密集的专家FFN工作放在物理上不同的资源池，MoE的dispatch/combine作为两者之间的通信层。本文贡献并非「AFD处处取胜」，而是一次严谨探索：何时AFD优于更简单的「预填充-解码解耦」、何时不优。实际意义：搭建MoE推理设备的厂商（Cerebras、Groq、FuriosaAI）在做硅片分区承诺之前，都需要这种设计空间分析。

Rotary GPU: exploring local execution paths for large MoE models under limited GPU memory Rotary GPU：在受限GPU内存下探索大MoE模型的本地执行路径 preprintMoEon-prem

co-authors not extracted

academic team

arXiv:2605.29135 · 2026-05-27

Asks an under-discussed question: once large MoE models exist, can they run usefully on the much smaller hardware that organizations under budget, security, or air-gap constraints actually have? Proposes a 'rotary' execution pattern that pages experts in and out of limited GPU memory rather than requiring resident parameter counts. Not glamorous, but practical — and tracks the same disaggregation thesis as the AFD work above, just from the on-prem-deployment angle rather than the hyperscaler angle. 提出一个被低估的问题：当大型MoE模型已经存在，它们能否在那些受预算、安全或气隙约束、硬件远小于超大规模客户的组织中跑出实用价值？论文提出一种「旋转」执行模式，把专家在有限GPU内存中分页换入换出，避免要求所有参数常驻。不性感但实用——与上面AFD工作指向同一解耦命题，只是切入点从超大规模客户变成本地部署。

Throughput-optimized networks at scale (Google TPU v4/5p case study) 规模下的吞吐量优化网络（Google TPU v4/5p案例） preprintTPUnetwork topology

Google infrastructure team

Google

arXiv:2605.27963 · 2026-05-27

Treats TPU v4/v5p topology, routing, and collectives as a joint optimization problem and shows the existing deployed networks leave 'terabytes per second' of throughput on the table. The work matters less for the specific TPU result and more for the methodology: this is the first paper to demonstrate that the reconfigurable-fabric design point can be optimized at scale with publishable end-to-end metrics. Watch for whether the same approach migrates to GB200 / Rubin NVL fabrics, where reconfigurability is more limited but the optimization opportunity is just as large. 把TPU v4/v5p的拓扑、路由与集合通信视作联合优化问题，并表明现有部署网络在吞吐量上存在「每秒TB级」的留白。本文意义不在TPU具体结果，而在方法论：这是首次有论文证明，可重构织物设计点在规模下可被优化、并发布端到端可比较指标。值得关注的是：同一方法能否迁移到可重构性更弱、但优化空间同样巨大的GB200／Rubin NVL织物。

Emerging Computing 新兴计算

MATBG Josephson diode as a universal thermal machine MATBG Josephson二极管作为通用热机 preprintMATBGquantum thermodynamics

co-authors not extracted

academic team

arXiv:2605.27560 · 2026-05-26

Magic-angle twisted bilayer graphene Josephson junctions with gate-tunable valley-polarized weak links implement quantum Stirling, Otto, and Carnot cycles — driven by the valley polarization potential rather than the usual superconducting phase bias. Distant from product silicon, but worth tracking because MATBG-based devices keep producing 'this shouldn't work this cleanly' results, and the device space that keeps doing that is the one to watch for the next decade's unexpected commercial substrate. 魔角扭曲双层石墨烯（MATBG）的Josephson结、配以可栅控的谷极化弱链路，实现量子Stirling、Otto与Carnot循环——以谷极化电位作为驱动参数，而非常规的超导相位偏置。距离量产硅片还很远，但值得关注：MATBG器件不断给出「不应该这么干净就成立」的结果，而这类持续给出此类结果的器件空间，正是值得观察的——下一个十年里那些意想不到的商用衬底很可能来自这里。

Induced nonlinear phase shift of forward-volume spin waves in YIG films and 1D magnonic crystals YIG薄膜与一维磁子晶体中前向体自旋波的诱导非线性相移 preprintmagnonicspin waves

co-authors not extracted

academic team

arXiv:2605.30206 · 2026-05-28

Demonstrates that forward-volume spin waves in perpendicularly-magnetized YIG films can be phase-shifted up to 180° by a co-propagating pumping wave at only a few milliwatts — a substantial improvement over surface-spin-wave equivalents and exactly the type of low-power nonlinearity magnonic computing needs to look credible. Still YIG-on-substrate physics rather than wafer-scale silicon, but the trajectory matters: magnonic logic gates have been one device-physics breakthrough away from credibility for a decade; this is the kind of result that closes that gap. 证明垂直磁化YIG薄膜中的前向体自旋波（SW），可被同向传播的泵浦波在仅几毫瓦功率下产生最多180°相移——这是相对于表面自旋波类似实验的实质性改进，恰恰是磁子计算需要的「低功耗非线性」。仍属YIG-on-衬底物理而非晶圆级硅工艺，但走势重要：磁子逻辑门十年来一直差「一次器件物理突破」即可获得可信度；这正是缩短此缺口的那类结果。