AI Accelerators & Compute-in-Memory
AI加速器与存算一体
L. Zheng, A. M. Bavani, M. Chen, et al.
IEEE Journal of Solid-State Circuits · 2026-09-01
PROTEUS is a 40 nm programmable digital CIM accelerator combining 4 Mb RRAM, 2.6 Mb tensor SRAM, and a 32-bit hierarchical ISA. It supports INT8, INT16, FP8, and FP16 execution and reports 702 GOPS, 6.4 TOPS/W, and 0.039 TOPS/mm². By storing micro-programs in RRAM, it can switch among preloaded kernels without off-chip instruction traffic or RRAM rewrites; the reported results cover CNNs, Transformers, GNNs, and state-space models.
PROTEUS是一款40 nm可编程数字CIM加速器，集成4 Mb RRAM、2.6 Mb tensor SRAM和32位分层ISA。它支持INT8、INT16、FP8和FP16运算，报告的性能为702 GOPS、6.4 TOPS/W和0.039 TOPS/mm²。通过把微程序存入RRAM，该设计可在预载内核之间切换而无需片外指令流或重写RRAM；实验覆盖CNN、Transformer、GNN和state-space model。
C.-T. Lin, J. Oh, M. Seok
IEEE Journal of Solid-State Circuits · 2026-09-01
STAR-SRAM implements a 16-bit BF16 SRAM-based digital CIM macro in 28 nm CMOS. Its designers combine model-based parameter selection with approximate multipliers and sparsity-aware wordline, clock, and input gating. The paper reports up to 43.06 TFLOPS/W, 1.89 TFLOPS/mm², and 400 Kb/mm², directly targeting the precision and density gap between low-bit CIM and modern neural workloads.
STAR-SRAM在28 nm CMOS中实现了基于SRAM的16位BF16数字CIM宏单元。设计团队结合基于模型的参数选择、近似乘法器，以及稀疏性感知的wordline、时钟和输入门控。论文报告最高43.06 TFLOPS/W、1.89 TFLOPS/mm²和400 Kb/mm²，直接瞄准低比特CIM与现代神经网络工作负载之间的精度和密度缺口。
I. Jung, J. Min, J.-Y. Kim
arXiv:2608.22613 · 2026-08-23
NOVA proposes a technology–architecture co-design for hybrid LLMs that combine grouped-query attention, state-space models, and MoE layers. It pairs a proposed 4F² vertical-channel DRAM cell and peri-over-cell structure, claimed to provide roughly 2× density at iso-area, with a near-memory architecture that adapts to disparate arithmetic intensities. The work is a preprint, so its density and system claims should be read as a proposed design rather than production silicon results.
NOVA提出了针对混合LLM的技术—架构协同设计，此类模型结合grouped-query attention、state-space model和MoE层。它将所提出的4F² vertical-channel DRAM单元及peri-over-cell结构——声称在等面积下约有2倍密度——与能适配不同算术强度的近存计算架构结合。该工作是预印本，因此其密度和系统主张应视为设计方案，而非量产硅片结果。
Devices & Process
器件与工艺
J.-K. Kim, D.-S. Woo, M.-J. Han, et al.
Advancement of science · 2026-08-25
This paper reports an electroforming-free, self-rectifying selector-only memory based on diffusive Cu-ion dynamics. The device combines diode-like unidirectional current with reported endurance near 10⁸ cycles and sub-20 ns self-rupturing conductive filaments. Eliminating high-voltage forming and reducing drift could address practical array concerns for 3D cross-point memory and logic-in-memory, although array-level integration remains the key test.
该论文报告了一种基于扩散Cu离子动力学的免电形成、自整流selector-only memory。该器件兼具类似二极管的单向电流，报告的耐久度接近10⁸次，并具有小于20 ns的导电细丝自断裂特性。免除高压forming并降低漂移，有望缓解3D cross-point memory和logic-in-memory的阵列实现难题，但阵列级集成仍是关键验证。
C.-H. Kim, M. S. Kim, J. B. Rhim, et al.
Advancement of science · 2026-08-25
The authors demonstrate wafer-scale monolithic 3D multi-valued logic using vertically stacked Te/IGZO heterojunction FETs and crystallinity-enhanced Te FETs. Interface and channel engineering stabilize an intrinsic ternary state using low-temperature CMOS-compatible processing. The result points to a route for higher logic density, but the architectural benefit depends on system-level support for ternary logic rather than device behavior alone.
作者利用垂直堆叠的Te/IGZO异质结FET和结晶性增强Te FET，展示了晶圆级单片3D多值逻辑。界面和沟道工程在低温CMOS兼容工艺下稳定了内禀三值状态。该结果指向更高逻辑密度的路径，但其架构收益还取决于系统级对三值逻辑的支持，而不仅是器件特性。
AI Systems & Inference
AI系统与推理
A. Taherin, S. Taghipour Anvari, C. Amante, et al.
arXiv:2608.25053 · 2026-08-25T18:43:43Z
Hydra provides a common-schema measurement framework for prefill and decode phases across three edge-SoC generations, 13 instruction-tuned LLMs, five execution formats, and two inference backends. Its released dataset contains roughly 107,000 per-prompt records combined with hardware telemetry. The analysis argues that latency averages conceal important effects from backend choice, quantization, memory traffic, and phase-specific utilization.
Hydra提供统一schema的测量框架，用于比较三代edge SoC、13个指令微调LLM、5种执行格式和两种推理后端上的prefill与decode阶段。其公开数据集包含约10.7万条逐prompt记录，并结合硬件遥测数据。分析指出，平均延迟掩盖了后端选择、量化、内存流量和阶段特定利用率带来的重要影响。
T. Lei, P. Katti, R. Dutt, et al.
arXiv:2608.21223 · 2026-08-21
This preprint proposes implicit perturbation for zeroth-order fine-tuning of spiking Transformers on in-memory-computing hardware. It combines perturbation terms with IMC weighted sums to avoid perturbation-induced read-modify-write operations, and exploits spike sparsity to reduce random-number-generator requirements. The idea addresses a hardware-specific obstacle in forward-only optimization, though its claimed benefits require validation on a complete accelerator implementation.
该预印本提出用于IMC硬件上脉冲Transformer zeroth-order微调的隐式扰动方法。它将扰动项与IMC加权和结合，以避免由扰动引起的read-modify-write操作，并利用脉冲稀疏性降低对随机数发生器的需求。该思路针对仅前向优化中的硬件特定障碍，但其所宣称的收益仍需在完整加速器实现上验证。
EDA & Design Automation
EDA与设计自动化
J. Zhou, Z. Shi, J. Zhu, et al.
arXiv:2608.28188 · 2026-08-28T10:56:04Z
DeepSeq3 represents a sequential circuit at two levels: combinational subgraphs divided by flip-flops and a super-node graph for register-transfer structure. A dual GNN is pre-trained to predict flip-flop-state reachability, capturing both local logic and temporal behavior. On the reported benchmarks, the framework reduces bounded-model-checking solve time by 18% while preserving correctness, though results remain limited to the evaluated designs.
DeepSeq3以两个层级表示时序电路：由flip-flop划分的组合子图，以及表达寄存器传输结构的super-node图。双GNN通过预测flip-flop状态可达性进行预训练，同时捕捉局部逻辑和时序行为。在报告的基准上，该框架在保持正确性的前提下将bounded model checking求解时间降低18%，但结果仍限于所评估的设计。
W. W. Xing, X. Zhou, K. Huang, et al.
arXiv:2608.26758 · 2026-08-27T07:53:18Z
HOLMES recasts failure-center localization for high-sigma yield estimation as few-shot binary classification using a tabular foundation model. It adds an SVD-based anisotropic sampling proposal and adaptive mixing to stabilize importance weights in high-dimensional SRAM problems. Across the authors' 6T SRAM cases from 108 to 1,152 dimensions, HOLMES reports relative error within 5.9%, compared with up to 25.8% for the strongest baseline.
HOLMES将high-sigma良率估计中的失效中心定位重构为few-shot二分类，并采用tabular foundation model进行in-context推理。它增加了基于SVD的各向异性采样proposal和自适应混合，以稳定高维SRAM问题中的importance weights。在作者的6T SRAM案例中，维度从108到1,152，HOLMES报告的相对误差不超过5.9%，而最强baseline最高达到25.8%。