Memory Movement Defines the Accelerator Research Stack 数据搬运定义加速器研究栈

This week’s papers treat memory capacity, dataflow, interconnect tuning and physical implementation as first-class AI-system constraints. The work ranges from near-memory LLM engines to 3D SRAM and reproducible 3D-IC design benchmarks. 本周论文将内存容量、数据流、互连调谐和物理实现视为 AI 系统的一等约束，覆盖近存 LLM 引擎、3D SRAM 以及可复现的 3D-IC 设计基准。

Look-back window: 7 days · 10 paper(s) 回溯窗口: 7天 · 10篇

Devices, Materials & Packaging 器件、材料与封装

Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM for 2 nm 面向 2 nm 的工艺感知型 Si/IGO 单片三维 6T SRAM

P.-C. Wang, D. Jang, E. Sarkar, et al.

arXiv:2608.22741 · 2026-08-24T02:59:37Z

This work proposes a monolithic-3D 6T SRAM that combines BEOL IGO pass gates with a silicon nanosheet latch, buried power rails and ruthenium interconnects. Its process-aware layout reports a 25% footprint reduction; at the 128×256 subarray level it reports 42.2% lower write delay versus a high-density silicon baseline, based on TCAD and extracted-parasitic analysis rather than fabricated silicon. 该工作提出一种单片三维 6T SRAM，将 BEOL IGO 传输门与硅纳米片锁存器、埋置电源轨和 Ru 互连结合。其工艺感知版图报告面积缩小 25%；在 128×256 子阵列层面，相比高密度硅基线写入延迟降低 42.2%，但结果基于 TCAD 与寄生参数提取分析，尚非实测芯片。

Circuits, Architecture & Reliability 电路、架构与可靠性

Architecting Asynchronous, Distributed GPUs for AI 面向 AI 的异步分布式 GPU 架构

J. Pan, W. An, C. Avalos Baddouh, et al.

arXiv:2608.22602 · 2026-08-23T21:19:17Z

The authors present a cycle-level framework for modern asynchronous, multi-chip GPUs and validate it against H100 silicon with 99% Pearson correlation and 13.4% mean absolute cycle error. They use it to study chiplet topology, larger SRAM capacity and bandwidth, and inter-GPU prefetching, offering a simulator rather than a new GPU implementation. 作者提出面向现代异步多芯粒 GPU 的周期级仿真框架，并以 H100 实硅验证，得到 99% 的 Pearson 相关系数和 13.4% 的平均绝对周期误差。该框架用于研究芯粒拓扑、更大的 SRAM 容量与带宽以及 GPU 间预取；其贡献是仿真基础设施，而非新的 GPU 实现。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

Maia 200: Software-Defined Dataflow for Large-Scale AI Maia 200：面向大规模 AI 的软件定义数据流

S. Xu, M. Heddes, J. Peng, et al.

arXiv:2608.24664 · 2026-08-25T15:05:40Z

Maia 200 describes a software-defined locally accessed dataflow architecture that explicitly programs data-movement engines and specialized memories. The paper reports 5,072 TFLOP/s FP8, 7 TB/s HBM bandwidth and a 750 W TDP, illustrating a design point where orchestration of data movement is treated as the central architectural resource. Maia 200 描述了一种软件定义的局部访问数据流架构，显式编程数据搬运引擎和专用存储器。论文报告其 FP8 性能为 5,072 TFLOP/s、HBM 带宽 7 TB/s、TDP 为 750 W，展示了将数据搬运编排视为核心架构资源的设计点。

NOVA Near-Memory Processing for Hybrid LLM Inference 用于混合 LLM 推理的 NOVA 近存计算

I.-J. Jung, J. Min, J.-Y. Kim

arXiv:2608.22613 · 2026-08-23T21:38:46Z

NOVA co-designs a near-memory processor for hybrid LLMs that combine grouped-query attention, state-space and MoE layers. It proposes a 4F² vertical-channel DRAM cell with peri-over-cell circuitry for roughly 2× iso-area density over a conventional 6F² cell, then adapts the architecture to layers with very different operational intensity; both the device and system claims need physical validation. NOVA 为结合 grouped-query attention、状态空间模型和 MoE 层的混合 LLM 协同设计近存处理器。它提出带有 peri-over-cell 电路的 4F² 垂直沟道 DRAM 单元，相比传统 6F² 单元在等面积下约提升 2 倍密度，并让架构适应运算强度差异很大的层；器件和系统层面的结论均有待实物验证。

FLINT: High-Bandwidth Flash for Capacity-Scalable LLM Inference FLINT：利用高带宽闪存实现可扩展容量的 LLM 推理

G. F. Oliveira, A. Tavakkol, X. Zhu, et al.

arXiv:2608.25062 · 2026-08-25T18:58:14Z

FLINT proposes a workload-driven substrate that uses emerging 3D-stacked high-bandwidth flash as a near-accelerator capacity tier alongside HBM. It targets microsecond flash-read latency, static prefetch limitations and flash-management operations exposed to the inference critical path, making capacity rather than only bandwidth a design variable for smaller LLM-serving nodes. FLINT 提出一种工作负载驱动的底层架构，将新兴的 3D 堆叠高带宽闪存作为 HBM 旁的近加速器容量层。它针对微秒级闪存读取延迟、静态预取的局限以及暴露在推理关键路径上的闪存管理操作，使容量而非仅带宽成为较小 LLM 服务节点的设计变量。

AI Systems & Hardware Co-Design AI系统与软硬件协同设计

APT: Attention-Guided Pruning and Quantization for Diffusion Transformers APT：面向 Diffusion Transformer 的注意力引导剪枝与量化

S. Yoo, S. Kim, J. Park, et al.

arXiv:2608.25380 · 2026-08-26T05:08:40Z

APT is a software-hardware co-design for high-resolution Diffusion Transformers that uses attention probabilities for both fine-grained pruning and adaptive precision assignment. It is designed to remain compatible with FlashAttention, addressing the steep attention cost as output resolution rises; the paper frames this as an accelerator design rather than a drop-in model-only compression method. APT 是面向高分辨率 Diffusion Transformer 的软硬件协同设计，利用注意力概率同时进行细粒度剪枝和自适应精度分配。它被设计为兼容 FlashAttention，以应对输出分辨率提高时急剧增长的注意力成本；论文将其定位为加速器设计，而非可直接替换的纯模型压缩方法。

Thermal Tuning in Wafer-Scale Optical Interconnects for MoE Training MoE 训练中晶圆级光互连的热调谐开销

S. Yoon, P.-J. Chen, S. Yu

arXiv:2608.24637 · 2026-08-25T14:48:53Z

This cross-layer study models wafer-scale DWDM optical links for MoE training, combining workload profiles, packet simulation and transient thermal analysis of a 3D GPU/EIC/PIC stack. It finds that thermal excursions can outpace conventional microring-resonator control loops and create repeated tuning stalls, then evaluates ferroelectric-based mitigation; the result highlights a system-level risk rather than a demonstrated production interconnect. 该跨层研究针对 MoE 训练建模晶圆级 DWDM 光链路，结合工作负载画像、分组仿真以及 3D GPU/EIC/PIC 堆栈的瞬态热分析。研究发现，温度波动可能超过传统微环谐振器控制环路的跟踪能力并造成反复调谐停顿，随后评估铁电缓解方案；其揭示的是系统级风险，而非已量产互连。

Electronic Design Automation 电子设计自动化

An Open-Source Benchmark Suite for 3D-IC Design 面向 3D-IC 设计的开源基准测试套件

R. Soni, J. Jeong, A. Graening, et al.

arXiv:2608.25155 · 2026-08-25T21:04:44Z

This paper releases an open-source suite of 3D-IC test cases derived from chiplet studies in the CATCH cost-estimation framework. The models span compute, memory, I/O, analog and substrate components and expose physical-design effects of TSVs, hybrid bonding and heterogeneous dies, providing reproducible inputs rather than a new placement algorithm. 论文发布了一套开源 3D-IC 测试用例，源自 CATCH 成本估算框架中的芯粒研究。模型覆盖计算、存储、I/O、模拟和衬底组件，并呈现 TSV、混合键合和异构裸片带来的物理设计效应，为研究提供可复现的输入，而非新的布局算法。

Syn2Logic: End-to-End Neuromorphic Design Automation Syn2Logic：端到端神经形态设计自动化

A. Podobas

arXiv:2608.25536 · 2026-08-26T08:49:02Z

Syn2Logic presents an electronic neuromorphic design-automation flow that compiles a domain-specific neural-behavior description into synthesizable RTL. The prototype reports a 5.6 million FPS/W accelerator on a small FPGA for MNIST and several application demonstrations, but the broad performance claims depend on the selected workloads and comparisons. Syn2Logic 提出一种电子神经形态设计自动化流程，可将领域专用的神经行为描述编译为可综合 RTL。原型在小型 FPGA 上针对 MNIST 报告 560 万 FPS/W，并展示多项应用；不过其广泛的性能主张取决于所选工作负载和比较基线。

Quantum & Unconventional Computing 量子与非常规计算

Langevin-Dynamics Hardware Annealing for Ising Machines 用于 Ising 机器的 Langevin 动力学硬件退火

Y. Liu, L. Sun, M. Huang, H. Wu

arXiv:2608.26100 · 2026-08-26T17:59:06Z