Circuits & Architecture
电路与架构
Qier Ma, Richard George, Stefan Scholze, et al.
arXiv:2608.20198 · 2026-08-20
A fabricated GF22FDX ASIC combines a quantized CNN engine with Pearson-correlation classification for real-time EEG auditory-attention decoding. The 2.09 mm² chip operates at 0.55 V, consumes 0.4941 mW and completes inference in 7.34 ms; the inference and classification engines occupy just 0.076 mm². The silicon results are relevant to always-on hearing assistance, although the preprint does not establish clinical performance at scale.
这款采用GF22FDX流片的ASIC把量化CNN引擎与Pearson相关分类器结合，用于实时EEG听觉注意力解码。芯片面积2.09 mm²，在0.55 V下功耗0.4941 mW、推理延迟7.34 ms，其中推理与分类引擎仅占0.076 mm²。实测硅结果适合始终在线的助听场景，但预印本尚未证明大规模临床效果。
Shreyas Srinivas, Ian W. Jones, Carsten Schulze, et al.
arXiv:2608.19954 · 2026-08-20
An all-digital circuit fabricated in IHP's 130 nm process detects voltage droops and adapts clock frequency while managing metastability in the detection path. The authors validate its operation on a test chip, moving the accompanying design beyond simulation. Quantitative response time and energy overhead are not included in the candidate abstract, so the practical guard-band savings remain to be assessed.
一款采用IHP 130 nm工艺流片的全数字电路可检测电压跌落并自适应调整时钟频率，同时处理检测路径中的亚稳态问题。作者在测试芯片上验证了功能，使配套设计从仿真走向实测。候选摘要未给出响应时间和能耗开销，因此实际可节省多少保护裕量仍需评估。
Abhishek Kumar, Seyed Hadi Mirfarshbafan, Oscar Castañeda, et al.
arXiv:2608.19865 · 2026-08-20
A fabricated 22FDX ASIC processes 16 OFDM subcarriers in parallel for an eight-user, 64-antenna massive-MIMO receiver. Exploiting beamspace sparsity and frequency-domain correlation cuts area and power by up to 3×; the 1.3 mm² core reaches 7.3 Gb/s at 286 mW and 0.8 V, or 39 pJ/b. The result is measured silicon, though comparison breadth beyond the claimed open-literature baseline is not shown in the candidate record.
这款22FDX流片ASIC面向8用户、64天线的大规模MIMO接收机，可并行处理16个OFDM子载波。利用波束空间稀疏性和频域相关性，面积与功耗最高降低3倍；1.3 mm²核心在0.8 V下以286 mW实现7.3 Gb/s，即39 pJ/b。结果来自实测硅片，但候选记录没有展示其与更广泛基线的比较范围。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Zihan Liu, Jingwen Leng, Yangjie Zhou, et al.
arXiv:2608.19628 · 2026-08-20
FIBER replaces fixed thread-private register ownership with lightweight execution instances that access an SM-wide shared register view. The ISA, microarchitecture and compiler co-design enables dynamic parallelism and fine-grained dataflow scheduling for workloads that mix GEMM and non-GEMM kernels. The proposal directly targets operand-supply inefficiency in modern tensor pipelines, but the candidate record is architecture work rather than a fabricated implementation.
FIBER以可访问SM级共享寄存器视图的轻量执行实例，取代固定的线程私有寄存器所有权。其ISA、微架构与编译器协同设计可为混合GEMM和非GEMM内核的负载提供动态并行度和细粒度数据流调度。该方案直指现代张量流水线的操作数供给效率，但候选记录属于架构研究，并非流片实现。
Jiahao Lin, Alish Kanani, Sangwan Lee, et al.
arXiv:2608.19395 · 2026-08-19
HYDRA jointly explores chiplet composition, physical placement, inter-chiplet bandwidth, batching and scheduling for Transformer-Mamba serving. Across the reported workloads it improves average throughput by 1.55× and cuts time to first token by 43.7%, with peak throughput gains of 2.3× over the selected baselines. The gains come from a Markov-based estimator and simulated design-space exploration, so hardware validation is still needed.
HYDRA面向Transformer-Mamba混合模型服务，联合探索chiplet组成、物理布局、片间带宽、批处理与调度。对报告中的负载，其平均吞吐量提高1.55倍，首token时间降低43.7%，相对所选基线的最高吞吐增益达2.3倍。结果依赖基于Markov模型的估算器和设计空间仿真，仍需真实硬件验证。
Peter Forcha, Harshitha Kajekusumadhar, Mbua Peter, et al.
arXiv:2608.18366 · 2026-08-18
MAGMA implements concurrent Gaussian-mixture inference and online expectation-maximization updates as a synthesizable fixed-point FPGA pipeline. On an AMD Spartan-7 it runs at 74.49 MHz using 7,779 LUTs and 91 DSPs with no block RAM, drawing 274 mW while reporting 11.8× inference and 81× M-step speedups over software. Adaptation accuracy is evaluated on a synthetic non-stationary scene, which limits conclusions about deployment robustness.
MAGMA把高斯混合模型推理和在线期望最大化更新实现为可综合的定点FPGA流水线。在AMD Spartan-7上，它以74.49 MHz运行，使用7,779个LUT和91个DSP、不占用块RAM，功耗274 mW；相对软件的推理和M步加速分别为11.8倍和81倍。其自适应准确率在合成非平稳场景上评估，因此对真实部署鲁棒性的结论仍有限。
Hardware-Relevant AI Research
硬件相关AI研究
Somashekar Manjunath, Rahul Ramachandra M
arXiv:2608.15764 · 2026-08-16
Microbenchmarks on three H100 SXM5 dies find plain ld.global bandwidth peaking near two offered loads per thread, then falling about 35% by eight loads. Fixed-work controls, reversed sweeps and a 512 MB-to-20 GB allocation range reproduce the decline while DRAM bytes stay nearly constant and L2-sector traffic rises. The clean-room result is actionable for memory-bound CUDA kernels, but it characterizes a narrow load path rather than the full Hopper memory system.
对3颗H100 SXM5芯片的微基准测试显示，普通ld.global带宽在线程每次约2个加载请求时达到峰值，到8个请求时下降约35%。固定工作量、反向扫描以及512 MB至20 GB分配范围的控制实验均复现该现象，同时DRAM字节量近乎不变而L2扇区流量上升。该净室测试对内存受限CUDA内核有直接参考价值，但只刻画了特定加载路径，并非完整的Hopper存储系统。
Hyojun Yun, Seungjae Won, Hyungpil Moon
arXiv:2608.15002 · 2026-08-15
An asynchronous training pipeline moves a frozen A8W8 INT8 visual encoder onto a Mobilint Aries2 NPU while an RTX 5060 Ti trains the FP32 action expert. Offloading the ResNet stage reduces energy per sample by 17.1% in the first configuration despite transfer and runtime overheads. The study uses 30,000-step robot-policy runs with three seeds, but the candidate abstract does not report whether deeper offload levels preserve the same benefit.
一个异步训练流水线把冻结的A8W8 INT8视觉编码器迁移到Mobilint Aries2 NPU，同时由RTX 5060 Ti训练FP32动作专家。第一种配置卸载ResNet阶段后，尽管存在传输和运行时开销，单样本能耗仍降低17.1%。研究使用3个随机种子完成30,000步机器人策略训练，但候选摘要未说明更深层卸载是否维持相同收益。