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Research digest · Thursday, August 13, 2026 研究摘要 · 2026年8月13日 星期四

Measured Hardware Grounds Neuromorphic Ambitions 实测硬件让神经形态计算落地

This week's strongest work moves beyond model-level claims into fabricated circuits, open implementation flows, and measured accelerator tradeoffs. The caveats remain visible: several demonstrations are small, workload-specific, or supported by simulation beyond the initial hardware proof. 本周较强的工作不再停留于模型层面,而是进入已制造电路、开放实现流程与实测加速器权衡。局限也很清楚:多项演示规模仍小、负载较窄,或在初步硬件验证之外仍依赖仿真。

Look-back window: 7 days · 8 paper(s) 回溯窗口: 7天 · 8篇

Devices & Process 器件与工艺

PbS Colloidal Quantum-Dot Imagers From Devices to CMOS Integration 从单器件到CMOS集成的PbS胶体量子点成像器

X. Hong, S. Zhang, R. Han, et al.

FlexMat · 2026-08-08

This review maps PbS colloidal quantum-dot imagers from band-structure engineering and defect passivation through flexible arrays and monolithic integration with CMOS readout circuits. Size-tunable bandgaps and solution processing could reduce the cost and integration complexity of visible-to-NIR imaging compared with conventional III-V approaches. It is a synthesis of prior results rather than a new measured array, so the value lies in its cross-layer comparison and remaining-manufacturability agenda. 这篇综述梳理了PbS胶体量子点成像器从能带工程、缺陷钝化,到柔性阵列及与CMOS读出电路单片集成的发展路径。可调带隙与溶液加工有望相较传统III-V方案降低可见光至近红外成像的成本与集成复杂度。该文是既有成果的综合而非新的实测阵列,其价值主要在于跨层比较以及对剩余制造问题的归纳。

Circuits & Architecture 电路与架构

High-Gain Readout for Low-Charge Semiconductor Detectors 面向低电荷半导体探测器的高增益读出电路

D. Zhang, K. Ma, J. Zhang, et al.

arXiv:2608.07963 · 2026-08-08

A three-stage SiGe:C-BJT and LTC6431 preamplifier board delivers 115.27 mV ns/fC charge gain across a 0.5-25 fC input range and 34.0-594.3 MHz bandwidth. Measurements with LGAD, PIN, and 3D silicon detectors reach timing resolutions of 36.41 ps, 76.10 ps, and 39.40 ps, respectively. The board is experimentally validated, but it is a discrete readout implementation rather than a monolithic front end. 这块三级前置放大板采用SiGe:C BJT与LTC6431,在0.5-25 fC输入范围内实现115.27 mV ns/fC电荷增益,带宽为34.0-594.3 MHz。搭配LGAD、PIN与3D硅探测器时,实测时间分辨率分别达到36.41 ps、76.10 ps与39.40 ps。该方案经过实验验证,但仍是分立式读出实现,并非单片集成前端。

Noise-Reconfigurable ECG Amplifier With 142.8-GOhm Input Impedance 输入阻抗142.8 GOhm的噪声可重构ECG放大器

H. Zheng, X. Liu

IEEE Journal of Solid-State Circuits · 2026-08-01

This chopper-stabilized ECG analog front end combines time-division multiplexing with new impedance-boosting and DC-servo loops to reach 142.8 GOhm input impedance. The ASIC can trade channel count against input-referred noise by reconfiguring among four-, two-, and one-channel modes. The design targets electrode-offset and leakage problems that often dominate wearable biopotential interfaces, with measured silicon reported in JSSC. 这款斩波稳定ECG模拟前端结合时分复用、新型阻抗提升环路与DC伺服环路,实现142.8 GOhm输入阻抗。ASIC可在4通道、2通道与1通道模式间重构,以通道数换取更低的输入参考噪声。设计针对可穿戴生物电接口中常见的电极失调与漏电问题,JSSC论文给出了实测芯片结果。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

A Memristive Neuron That Learns on Chip 可在芯片上学习的忆阻神经元

N. Jimenez Olalla, A. Long Ching Ip, M. Baumann, et al.

Neuromorphic Computing and Engineering · 2026-08-06

A physical memristor-and-op-amp neuron implements a biologically inspired local learning rule and learns XOR, AND, and OR in a small network. Moving adaptation into the circuit addresses a core limitation of neuromorphic systems that still depend on offline software training. The hardware proof is limited to elementary logic; the compressed-MNIST scaling result comes from SPICE rather than a larger fabricated network. 一个由忆阻器与运算放大器构成的物理神经元实现了受生物机制启发的局部学习规则,并在小型网络中学会XOR、AND与OR。把适应过程放入电路,可直接触及当前神经形态系统仍依赖离线软件训练的核心限制。硬件验证仅覆盖基础逻辑,压缩MNIST的扩展结果仍来自SPICE仿真,而非更大规模的已制造网络。

A Client-Side CKKS Accelerator With Dynamic Twiddle Generation 采用动态旋转因子生成的客户端CKKS加速器

P. Sun, M. Ikeda

IEEE Transactions on VLSI Systems · 2026-08-01

This accelerator targets the less-studied client side of CKKS homomorphic encryption, unifying NTT and FFT multiplication while generating twiddle factors dynamically instead of storing large tables. Evaluations on a TSMC 28 nm ASIC and Xilinx UltraScale+ FPGA show more than 40% lower area or gate count and a 1.2x end-to-end speedup against representative hardware baselines. The gains are practical but moderate at system level, making the memory and area reductions as important as raw latency. 该加速器面向研究较少的CKKS同态加密客户端,将NTT与FFT乘法统一,并动态生成旋转因子,从而避免存储大型常量表。在TSMC 28 nm ASIC与Xilinx UltraScale+ FPGA上的评估显示,相较代表性硬件基线,面积或门数降低超过40%,端到端速度提升1.2倍。系统级速度增益较为温和,因此存储与面积节省与延迟改善同样重要。

SYNtzulA Open Hardware for Near-Sensor SNN Inference 用于近传感器SNN推理的SYNtzulA开放硬件

L. Martis, G. Leone, L. Raffo, et al.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2026-08-01

SYNtzulA integrates a RISC-V soft core and sparse SNN accelerator in a 6.8 mm2 SoC built with the open IHP-SG13G2 130 nm PDK and OpenROAD flow. The chip runs at up to 125 MHz, reaches 2 GSOP/s, and reports 36.5 pJ per synaptic operation. Its older node and modest throughput limit direct comparison with commercial neuromorphic processors, but silicon from a fully open flow makes the platform unusually reproducible. SYNtzulA在6.8 mm2 SoC中集成RISC-V软核与稀疏SNN加速器,采用开放的IHP-SG13G2 130 nm PDK和OpenROAD流程实现。芯片最高运行于125 MHz,达到2 GSOP/s,单次突触操作能耗为36.5 pJ。较老制程与有限吞吐量使其难以直接对标商用神经形态处理器,但完全开放流程产出的实测芯片具备少见的可复现性。

Time-Multiplexed FPGA SNN Accelerator With Pipelined Readout 采用流水线读出的时分复用FPGA SNN加速器

R. Ansari, M. Wielgosz

arXiv:2608.00595 · 2026-08-01

A time-multiplexed spike feeder, localized weight memories, and pipelined argmax readout raise an Artix-7 SNN accelerator's maximum clock from 13.3 MHz to 167 MHz. The measured implementation processes an image in 82 microseconds using a 784-64-10 network. The large frequency gain addresses a real routing bottleneck, but MNIST and the small topology leave efficiency on modern workloads unresolved. 通过时分复用脉冲输入、本地化权重存储与流水线argmax读出,这款Artix-7 SNN加速器的最高频率从13.3 MHz提升至167 MHz。实测实现采用784-64-10网络,单张图像处理延迟为82微秒。频率提升解决了真实的布线关键路径,但MNIST与小型网络拓扑仍不足以说明其在现代工作负载上的效率。

EDA & Design Tools EDA与设计工具

Open, Silicon-Verified Asynchronous Periphery for Neuromorphic Chips 面向神经形态芯片的开放式实硅验证异步外围电路

H. Greatorex, M. Cotteret, M. Mastella, et al.

International Conference on Systems · 2026-08-04

This work releases reusable asynchronous peripheral circuits for mixed-signal neuromorphic processors using ACT, quasi-delay-insensitive design, and dual-rail encoding. The library is validated from behavioral models through fabricated-silicon timing measurements, addressing a practical block that many research groups currently redesign from scratch. Its impact will depend on portability across processes and interfaces, but silicon verification makes it more useful than a template-only release. 该工作发布了一套可复用的混合信号神经形态处理器异步外围电路,采用ACT、准延迟无关设计与双轨编码。其验证覆盖行为模型到已制造芯片的时序测量,针对许多研究团队目前需要重复设计的实际障碍。该库的影响力仍取决于跨制程与接口的可移植性,但实硅验证使其价值高于仅提供模板的开源项目。

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