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Research digest · Sunday, August 9, 2026 研究摘要 · 2026年8月9日 星期日

Memory systems become the accelerator 存储系统正在成为加速器

This week's papers move memory management, low-precision formats, and near-memory execution into the center of AI-system design. At the same time, measurement and EDA work targets the tools needed to validate those increasingly complex systems. 本周论文将存储管理、低精度格式与近存计算推到AI系统设计的核心位置。与此同时，测量与EDA研究也在完善验证这些日益复杂系统所需的工具链。

Look-back window: 7 days · 9 paper(s) 回溯窗口: 7天 · 9篇

Devices & Process 器件与工艺

CMOS-compatible bismuth photodetector for SWIR silicon waveguides 面向短波红外硅波导的CMOS兼容铋光电探测器

Liqiang Qi, Jiaqi Wang, Zhibin Yang, et al.

ACS Photonics · 2026-08-06

The authors directly grow a two-dimensional bismuth film at low temperature in a back-end CMOS-compatible flow to make a waveguide-integrated SWIR detector. At 2200 nm, the device reports about 2 dB/μm absorption, 185.3 mA/W responsivity, and 201.4 nA dark current. Transfer-free growth could make wafer-scale integration more practical, although performance will still need to be tested across full process variation and packaging conditions. 作者采用与CMOS后段工艺兼容的低温直接生长方法，在硅波导上制备二维铋短波红外探测器。器件在2200nm处报告约2 dB/μm吸收系数、185.3 mA/W响应度和201.4 nA暗电流。免转移生长有望提升晶圆级集成可制造性，但仍需在完整工艺波动和封装条件下验证其性能。

Controlling self-focusing in femtosecond slicing of 4H-SiC wafers 4H-SiC晶圆飞秒激光切片中的自聚焦控制

Dong Hee Kang, Jaeseung Lim, Mishfaqur Rahman, et al.

arXiv:2608.03814 · 2026-08-04

This work links Kerr-induced self-focusing during femtosecond laser slicing of 4H-SiC to pulse energy, processing depth, surface texture, and separation stress. The result provides a process-control route for producing thin SiC layers, which are increasingly relevant to power devices and heterogeneous integration. Its practical value will depend on throughput, yield, and equipment repeatability beyond the reported experiments. 该研究将4H-SiC飞秒激光切片中的Kerr效应自聚焦与脉冲能量、加工深度、表面纹理和分离应力关联起来。结果为制备薄型SiC层提供了工艺控制路径，这对功率器件和异构集成日益重要。其工程价值仍取决于实验之外的吞吐量、良率与设备重复性。

Circuits & Systems 电路与系统

PowerScope: ML-based intra-cycle power estimation PowerScope：基于机器学习的周期内功耗估计

Jayanth Balasubramanian, Sujay Pandit, Radha Vaidya, et al.

arXiv:2608.05339 · 2026-08-05

PowerScope estimates sub-cycle power directly from RTL simulation traces, avoiding per-workload post-layout gate-level analysis. Across its benchmark suite, it reports 5.88% median and 9% mean absolute percentage error versus commercial post-layout estimates while running roughly 80 times faster. That could shorten PDN and voltage-droop iteration, but the reported accuracy must transfer to new libraries and physical-design flows to be broadly useful. PowerScope直接从RTL仿真轨迹估计子周期功耗，避免逐工作负载执行后布局门级功耗分析。在其基准套件上，系统相对商业后布局估计的中位绝对百分比误差为5.88%、平均误差为9%，速度约快80倍。这可能缩短PDN和压降分析迭代，但其准确性仍需迁移到新的标准单元库和物理设计流程中验证。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

PLoRA: pooled near-data memory for multi-LoRA serving PLoRA：用于多LoRA服务的近数据池化内存

Zhongkai Yu, Ohm Rishabh Venkatachalam, Zheng Wang, et al.

arXiv:2608.05483 · 2026-08-06

PLoRA proposes placing LoRA adapters and KV cache in pooled memory with near-data processing, returning reduced results rather than repeatedly staging adapters through CPU DRAM and PCIe. Its runtime chooses among execution and caching strategies per adapter. The design directly addresses the memory-heavy nature of serving thousands of specialized adapters, but it depends on the availability and software maturity of coherent pooled-memory fabrics. PLoRA提出将LoRA适配器和KV Cache置于带近数据处理能力的池化内存中，只返回规约结果，而非反复经由CPU DRAM和PCIe搬运适配器。其运行时会针对每个适配器选择执行与缓存策略。该设计直指数千个专用适配器服务的存储瓶颈，但依赖于一致性池化内存互连的可用性和软件成熟度。

KARAT splits sparse-attention serving across GPUs and processing-near-memory KARAT将稀疏注意力服务拆分至GPU与近存计算节点

Hyungkyu Ham, Junhyeong Bae, Seungheon Lee, et al.

arXiv:2608.03555 · 2026-08-04

KARAT keeps model weights and projection or MoE work on GPUs while placing KV cache, retrieval indices, and their memory-reading operations on processing-near-memory nodes. The heterogeneous split is designed for retrieval-based sparse attention at very long context lengths. It is a useful architectural direction, although its benefit will hinge on link latency, scheduling overhead, and how quickly sparse-attention algorithms change. KARAT将模型权重以及投影和MoE计算保留在GPU上，把KV Cache、检索索引及相应的内存读取操作放到近存计算节点。该异构划分针对超长上下文的检索式稀疏注意力设计。这是一条有价值的架构路径，但其收益取决于互连延迟、调度开销以及稀疏注意力算法的演进速度。

Chebyshev systolic array unifies activation and softmax approximation 基于Chebyshev的脉动阵列统一激活函数与Softmax近似

Benedikt Schaible, Anirudh Suresh Bharadwaj, Ulf Schlichtmann, et al.

arXiv:2608.04734 · 2026-08-05

The paper uses Chebyshev-polynomial approximations in a systolic-array unit that handles both nonlinear activations and softmax. It reports up to 71% lower tanh mean absolute error than a CORDIC baseline with 4.6% less area and 5.1% less power, plus lower softmax KL divergence. Sharing hardware across these functions can improve accelerator utilization, though approximation quality remains workload and precision dependent. 论文用Chebyshev多项式近似构建脉动阵列单元，同时处理非线性激活函数和Softmax。相对CORDIC基线，作者报告tanh平均绝对误差最高降低71%，面积减少4.6%、功耗降低5.1%，Softmax的KL散度也更低。跨函数共享硬件可提升加速器利用率，但近似精度仍取决于工作负载和数值精度。

AI Systems & Models AI系统与模型

AdaMX: heterogeneity-aware microscaling for low-bit LLM inference AdaMX：面向低比特LLM推理的异构感知微缩放

Junyi Luo, Xinting Jiang, Tai-Hao Wen, et al.

arXiv:2608.03867 · 2026-08-04

AdaMX varies both the representation and precision-recovery scheme across quantization blocks and between weights and activations, rather than applying one MXFP4 treatment everywhere. The authors implement a 22 nm FD-SOI accelerator prototype and report about 1% system-energy overhead versus an otherwise identical MXFP4 design. The proposition is compelling because it targets accuracy lost to fixed formats, but its gains need comparison across models and production compiler stacks. AdaMX不再对所有量化块统一采用一种MXFP4处理方式，而是分别调整表示格式和精度恢复方案，并区分权重与激活值。作者实现了22nm FD-SOI加速器原型，相比其他条件相同的MXFP4设计，系统能耗开销约为1%。该方法直指固定格式带来的精度损失，但其收益仍需在更多模型和生产级编译器栈上比较。

EDA & Design Automation EDA与设计自动化

EDATracer: evidence-grounded analysis across EDA artifacts EDATracer：跨EDA工件的证据可追溯分析

Phat Tieu, Sayanti Jana, Matthew DeLorenzo, et al.

arXiv:2608.04032 · 2026-08-02

EDATracer combines a knowledge graph and vector index to let agents retrieve evidence across RTL and source files, scripts, logs, netlists, and reports. Its new dataset contains 18.9 GB from 2,787 synthesizable open-source designs and a 90-question benchmark; the paper reports average pass@1 gains of 6.4 and 7.2 percentage points over Cursor and Claude Code. The benchmark is a meaningful step toward auditable EDA agents, though performance on proprietary flows and tool outputs remains an open question. EDATracer结合知识图谱与向量索引，使智能体能够跨RTL和源文件、脚本、日志、网表及报告检索证据。其新数据集包含来自2,787个可综合开源设计的18.9GB数据，并提供90道题的基准；论文报告其平均pass@1比Cursor和Claude Code分别高6.4和7.2个百分点。该基准推动EDA智能体走向可审计，但在专有流程和工具输出上的表现仍有待验证。

Quantum Computing 量子计算

Ant-Q addresses the control-memory bottleneck in quantum experiments Ant-Q缓解量子实验中的控制存储瓶颈

Yicheng Guang, Neel Vora, Yilun Xu, et al.

arXiv:2608.06318 · 2026-08-06

Ant-Q combines DRAM and on-chip BRAM in a memory hierarchy intended to preserve deterministic timing while pipelining quantum-circuit execution. Across 26 experimental and computing circuits, the authors report reducing circuit-loading and readout-uplink overhead relative to execution time from 22.90–1417.05% to near zero. The work identifies control electronics as a throughput limiter, though integration into QubiC 3.0 will be the more consequential test of its real-world impact. Ant-Q将DRAM与片上BRAM组合成存储层级，旨在在流水化执行量子电路时保持确定性时序。作者在26个实验和计算电路上报告，将相对执行时间为22.90%至1417.05%的电路加载与读出上行开销降至接近零。该研究指出控制电子学是吞吐量限制因素，但其集成到QubiC 3.0后的表现才是更关键的实际检验。

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