Making Compute Systems More Physically Aware 让计算系统更具物理感知能力

This week’s papers connect hardware efficiency to physical constraints: photonic loss, transistor hotspots, three-dimensional atom transport, and layout power. The common goal is to move optimization closer to device and system behavior. 本周论文将硬件效率与物理约束联系起来，包括光子损耗、晶体管热点、三维原子搬运和版图功耗。它们的共同目标是让优化更贴近器件和系统行为。

Look-back window: 7 days · 6 paper(s) 回溯窗口: 7天 · 6篇

Devices & Process 器件与工艺

Foundry-compatible silicon-photonics MEMS optical switch 兼容晶圆厂工艺的硅光MEMS光开关

Arkadev Roy, Daniel Klawson, Jianheng Luo, et al.

arXiv:2608.03146 · 2026-08-04T05:23:12Z

The authors demonstrate a C-band silicon-photonics MEMS switch made in a zero-change foundry-compatible flow with BEOL post-processing. It reports more than 30 dB extinction, under 1.5 dB insertion loss, and roughly 20 nW static power, a strong combination if endurance and array integration hold up. 作者展示了一种采用零改动、兼容晶圆厂流程并结合BEOL后处理的C波段硅光MEMS光开关。该器件报告超过30 dB消光比、低于1.5 dB插入损耗和约20 nW静态功耗；若耐久性和阵列集成表现可靠，这一组合颇具吸引力。

Active passivation steers hotspots in GaN transistors 主动钝化调控GaN晶体管热点位置

Yicheng Wei, Sihang Liu, Zimu Jiang, et al.

arXiv:2608.01257 · 2026-08-02T14:06:53Z

This work uses active-passivation length to shift the hotspot in GaN transistors from the gate edge to the drain-side passivation edge. Micro-Raman thermography and multiphysics simulation tie the movement to peak electric field and localized Joule heating, offering a lever for power-device thermal reliability. 该研究通过改变主动钝化层长度，将GaN晶体管热点从栅极边缘转移至漏极侧钝化层边缘。微拉曼测温和多物理场仿真将这一迁移与峰值电场及局部焦耳热相关联，为功率器件热可靠性提供了设计手段。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

FPGA partial reconfiguration for LLM nonlinear functions 利用FPGA局部重构实现LLM非线性函数计算

Roger Morales-Monge, Nazareth Jimenez-Chacon, Jose Gabriel Villalobos-Alvarado, et al.

arXiv:2608.03033 · 2026-08-04T02:27:48Z

The paper uses FPGA partial reconfiguration to swap piecewise-linear exponential and sigmoid units for LLM acceleration. Compared with a static design holding both operators, it reports up to 43% fewer LUTs and up to 50% fewer flip-flops, BRAMs, and DSPs, subject to reconfiguration overhead in real workloads. 论文利用FPGA局部重构来切换面向LLM加速的分段线性指数和sigmoid单元。相对于同时固定集成两种算子的静态设计，它报告最多减少43%的LUT，并最多减少50%的触发器、BRAM和DSP，但真实工作负载仍要考虑重构开销。

Celty co-designs a sparse GPU path for LLM decoding Celty为LLM解码协同设计稀疏GPU执行路径

Ruokai Yin, Priyadarshini Panda

arXiv:2608.01536 · 2026-08-02T23:10:04Z

Celty targets single-user LLM decoding with both pruned weights and runtime activation sparsity, a case conventional GPU kernels handle poorly. Its compressed format, kernel, and proposed SIMT core work together to avoid index reconstruction and memory traffic; the benefit will depend on attainable sparsity and hardware adoption. Celty面向同时具有剪枝权重和运行时激活稀疏性的单用户LLM解码，这类工作负载通常难以被传统GPU内核高效处理。其压缩格式、内核和拟议SIMT核心协同设计，以避免索引重建和多余内存访问；实际收益取决于可实现稀疏度及硬件采用。

Electronic Design Automation 电子设计自动化

Fovea brings physical constraints into wafer-scale design exploration Fovea将物理约束纳入晶圆级设计空间探索

Jinxi Li, Huizheng Wang, Jinyi Deng, et al.

arXiv:2608.03285 · 2026-08-04T08:00:29Z

Fovea formulates wafer-scale architecture exploration around coupled constraints including reticle compliance, wafer tiling, die area, die-to-die capability, and placement. It calibrates disagreement between low-cost and reference evaluators before refinement, reducing the risk that a fixed coarse shortlist misses full-fidelity winners. Fovea围绕光罩合规、晶圆平铺、芯粒面积、芯粒间互连能力和布局等耦合约束来构建设计空间。它在细化候选方案前校准低成本评估器与参考评估器之间的偏差，从而降低固定粗筛名单漏掉全保真优胜设计的风险。

Quantum Computing 量子计算

Piqasso compiles for three-dimensional neutral-atom computers Piqasso面向三维中性原子量子计算机进行编译

Chen Huang, Zhemin Zhang, Zhao Zhang, et al.

arXiv:2608.01316 · 2026-08-02T15:34:47Z

Piqasso compiles for three-dimensional neutral-atom arrays by separating storage, entanglement, and readout into layers, then routing atoms with vertical hops and multi-AOD scheduling. Across 34 circuits it reports 2.1× less transport distance, up to 7.3× faster execution, 2.2× higher movement fidelity, and 1.8× fewer serialized transport rounds than a planar baseline. Piqasso面向三维中性原子阵列进行编译，将存储、纠缠和读出分置于不同层，并通过垂直搬运和多AOD调度完成原子路由。在34个电路上，它相对于平面基线报告2.1倍更短的搬运距离、最高7.3倍更快执行、2.2倍更高移动保真度和1.8倍更少的串行搬运轮次。