Circuits & Architecture
电路与体系结构
Yanxin Zhang, Shayne Wadle, Yuxuan Xiong, et al.
arXiv:2608.01041 · 2026-08-02T06:55:43Z
The authors find that ML performance predictors can rank structural hardware settings well in aggregate yet miss counter-intuitive execution windows. Such windows make up 22.4% of non-tied cases in the study, cautioning against using fast predictors as final policy selectors.
作者发现，机器学习性能预测器可在总体上较好地排序硬件结构设置，却会错过反直觉的执行窗口。此类窗口占研究中非平局情形的22.4%，因此不宜把快速预测器直接作为最终策略选择器。
Yanxin Zhang, Ian McDougall, Junnan Li, et al.
arXiv:2608.01038 · 2026-08-02T06:49:51Z
A composition study across 490 phases finds that the best global static prefetcher-and-replacement stack still trails a phase oracle by 1.33%. A selector changing only the L1D prefetcher can come within 0.039% IPC of an eight-configuration oracle, suggesting a narrow control interface.
一项覆盖490个阶段的组合研究发现，最佳全局静态预取与替换策略组合仍比阶段预言机低1.33%。仅切换L1D预取器的选择器即可达到距八配置预言机0.039% IPC以内，说明可以采用范围有限的控制接口。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Ruijie Gao, Jirong Yang, Barry Lyu, et al.
arXiv:2608.00894 · 2026-08-01T23:22:04Z
Zomboss moves accelerator semantics and legality constraints into a reusable compiler artifact, leaving a neural agent to search workload-specific mappings. It returns verified kernels on all 56 Gemmini and PLENA instances and reports 3.34× geometric-mean speedup over the Gemmini compiler default.
Zomboss将加速器语义和合法性约束编译为可复用工件，让神经代理只搜索工作负载相关的映射。它在56个Gemmini和PLENA实例上均返回已验证内核，并报告相对Gemmini编译器默认方案3.34倍的几何平均加速。
Conor James Green, William Won, Tuan Ta, Bradford M. Beckmann
arXiv:2608.00867 · 2026-08-01T21:01:52Z
NUNA treats physical position inside large multi-die GPU systems as a network-locality problem for collective communication. Placement plus routing achieves up to 1.8× faster collectives and a 7% mean time-per-output-token improvement in the evaluated inference workloads.
NUNA将大型多芯粒GPU系统中的物理位置视为集体通信的网络局部性问题。放置与路由结合后，在所评估的推理工作负载上实现最高1.8倍的集体通信加速，以及平均7%的每输出token时间改善。
Oliver Cassidy, Marta Andronic, George A. Constantinides
arXiv:2608.00720 · 2026-08-01T15:40:13Z
CascadeLUT orders features so LUT-based FPGA models can refine predictions as data arrives instead of buffering a full sample. It reports 4.0–12.5× lower latency and up to 13.8× lower energy per sample than its LUT baselines, trading extra LUT use for less data movement.
CascadeLUT对特征排序，使基于查找表的FPGA模型能在数据到达时逐步优化预测，而无需缓存完整样本。它相对其LUT基线报告4.0至12.5倍更低时延及最高13.8倍更低的单样本能耗，以更多LUT资源换取更少的数据移动。