Devices & Process
器件与工艺
Jongseon Seo, Geonhui Han, Laeyong Jung, et al.
IEEE Electron Device Letters · 2026-08-01
The authors add an ultrathin ozone-oxidized barrier to a WO3−x/HfOx ionic-FET ECRAM stack to suppress ion back-diffusion without blocking useful ion injection. They report a roughly 7.6-V memory window, stable 3-bit operation, and endurance above 10^5 program/erase cycles; retention above 10^6 is a room-temperature projection that still needs system-level validation.
作者在WO3−x/HfOx离子FET ECRAM堆栈中加入超薄臭氧氧化阻挡层，以抑制离子回扩散，同时保留有效的离子注入。器件报告约7.6 V存储窗、稳定的3 bit操作和超过10^5次的写擦耐久度；超过10^6的室温保持时间为推算值，仍需系统级验证。
Wenjuan Zhou, Ruizhan Yan, Renhao Xue, Mansun Chan, Xiwen Liu
IEEE Electron Device Letters · 2026-08-01
This work experimentally demonstrates a monolithic five-layer cross-point-memory stack using hafnia-based ferroelectric diodes and an all-ALD process. The approximately 10-nm-per-tier stack reaches an ON/OFF ratio near 10^3, nonlinearity up to about 600, 50-ns programming, and endurance beyond 10^7 cycles, directly addressing selector and layer-uniformity limits in vertical memory.
该研究实验演示了采用HfO2基铁电二极管和全ALD工艺的单片五层交叉点存储堆栈。该堆栈每层约10 nm，实现约10^3的开关比、最高约600的非线性度、50 ns编程和超过10^7次耐久度，直接应对垂直存储中的选通器与层间均匀性难题。
Sheung Hun Kim, Youngkeun Park, Batzorig Buyantogtokh, et al.
IEEE Electron Device Letters · 2026-08-01
The study replaces conventional HfZrO2 with La-doped HfO2 in a ferroelectric FET and reports 2Pr of 47.8 μC/cm². Relative to HfZrO2 devices, the La-doped FeFETs show a 16.0% wider memory window and smaller threshold shifts during disturb cycling, making the material choice relevant to dense nonvolatile-memory arrays.
研究以La掺杂HfO2替代传统HfZrO2作为铁电FET层，并报告47.8 μC/cm²的2Pr。与HfZrO2器件相比，La掺杂FeFET的存储窗扩大16.0%，且在扰动循环中的阈值漂移更小，因此该材料选择对高密度非易失存储阵列具有意义。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
S. Q. Yan, J. Wang, S. Liu, et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2026-08-01
This 40-nm CMOS compute-in-memory macro reuses its capacitor array for charge-domain MACs and SAR conversion, then combines quantization storage with in-memory serial accumulation. The authors report a 44% transistor-count reduction, up to 250.73 TOPS/W and 255.5 GOPS, with selectable 1-, 2-, and 4-bit signed or unsigned weights; reported task accuracy remains below full-precision baselines on CIFAR-10.
这款40 nm CMOS存算一体宏复用电容阵列完成电荷域MAC和SAR转换，并把量化结果存储与存内串行累加结合。作者报告晶体管数量减少44%、最高250.73 TOPS/W和255.5 GOPS，并支持1、2、4 bit有符号或无符号权重；其在CIFAR-10上的报告精度仍低于全精度基线。
Zhoujie Pan, Yuwan Hong, Dingyi Zhang, Yanming Liu, He Tian
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2026-08-01
The paper proposes a MoS2-transistor-enhanced antisymmetric 2T2R in-memory XNOR cell that completes write and compute in one step for binary neural-network workloads. It argues that the device choice can reduce static power and support monolithic 3D integration, while the BNN mapping makes quantization error an explicit system-level trade-off.
论文提出一种由MoS2晶体管增强的非对称2T2R存内XNOR单元，可针对二值神经网络在一步内完成写入与计算。作者认为该器件选择能降低静态功耗并支持单片三维集成，同时配套的BNN映射把量化误差作为明确的系统级权衡。