AI Accelerators & Compute-in-Memory
AI加速器与存算一体
J. Mensing, W. G. van der Wiel, A. Heuer
arXiv:2607.27844 · 2026-07-30
The authors turn metallic nanoparticles linked by molecular junctions on SiO2/Si into a tunable nonlinear reservoir by surrounding them with control electrodes. Their analysis identifies operating frequency, oxide thickness, and junction disorder as design levers for balancing tunneling nonlinearity against memory. It offers useful physical rules for reservoir hardware, although the paper's computational benefits will depend on reproducibility across fabricated networks.
作者在SiO2/Si衬底上利用分子结连接金属纳米颗粒，并通过周围控制电极将其转化为可调非线性储备池。研究指出工作频率、氧化层厚度和结的无序度是平衡隧穿非线性与记忆特性的关键设计变量。该工作为储备池硬件提供了有用的物理设计规则，但其计算收益仍取决于不同制造网络之间的可重复性。
B. Wang, C. Zhang, D. Shen, et al.
arXiv:2607.25504 · 2026-07-28
Ventaglio adds a configurable sparse-execution unit and RVV extensions for indexed gather-accumulate-scatter operations used in Transformer inference. In a 12 nm open-source vector cluster, the design reports 6.9–7.4× faster sparse contractions than optimized RVV baselines for a 3.1% cluster-area overhead. The results make a strong architectural case, but their system-level value depends on workloads retaining enough structured sparsity to amortize metadata handling.
Ventaglio为Transformer推理中的索引式gather-accumulate-scatter操作加入可配置稀疏执行单元和RVV扩展。在12 nm开源向量集群中，设计相对优化RVV基线实现了6.9–7.4倍的稀疏张量收缩加速，集群面积开销为3.1%。结果有力支持该架构思路，但系统层面的收益仍取决于工作负载能否保持足够的结构化稀疏性，以摊薄元数据处理成本。
M. Brazzini, G. Filippeschi, A. Catania, et al.
arXiv:2607.25058 · 2026-07-27
This paper combines circuit-level compensation with batch-normalization recalibration to offset retention loss in a 65 nm single-poly floating-gate analog CIM array. With a retention model calibrated to experiments, the authors recover baseline inference accuracy to within 2–4% after 60 days on VGG-10 and WideResNet workloads. It directly addresses a practical deployment problem, though the result leaves endurance, reprogramming overhead, and broader model coverage to be quantified.
论文将电路级补偿与batch normalization重校准结合，用于抵消65 nm单层多晶硅浮栅模拟存算一体阵列的保持损失。基于实验校准的保持模型，作者在VGG-10和WideResNet任务上将编程60天后的推理精度恢复到距基线2–4%以内。该研究直面实际部署难题，但耐久性、重编程开销和更广泛模型覆盖仍有待量化。
AI Systems & Inference
AI系统与推理
S. Kim, Y. Choi, B. Kim, et al.
arXiv:2607.27694 · 2026-07-30
GyRot co-designs coarse rotation, fine-grained grouping, and integer dequantization to avoid the mismatch between global rotations and local quantization scales. Its INT4 tensor-processing element reports up to 3.4× speedup and 3.6× energy efficiency over baseline LLM accelerators while maintaining leading 4-bit LLaMA-family accuracy. The claims are promising, but comparison against production quantization stacks and complete memory-system costs will determine portability.
GyRot协同设计粗粒度旋转、细粒度分组和整数反量化，以避免全局旋转与局部量化尺度之间的不匹配。其INT4张量处理单元在保持LLaMA系列领先4 bit精度的同时，相对基线LLM加速器报告最高3.4倍加速和3.6倍能效提升。结果颇具潜力，但与生产级量化栈及完整存储系统成本的比较将决定其可移植性。
J. Yang, J. Li, Y. Fu, et al.
arXiv:2607.25498 · 2026-07-28
DOPS schedules LLM operators across heterogeneous NPU and processing-in-memory systems while also choosing blockwise weight layouts under memory constraints. The Bifocal scheduler achieves a 1.20–2.23× geometric-mean speedup over a prefill–decode baseline, and layout selection adds a further 1.28–1.33×. The framework is useful because it treats contention and weight placement as first-class factors, although it needs validation on commercially deployed heterogeneous servers.
DOPS在异构NPU与processing-in-memory系统之间调度LLM算子，同时在内存约束下选择分块权重布局。Bifocal调度器相对prefill–decode基线取得1.20–2.23倍几何平均加速，布局选择再带来1.28–1.33倍提升。该框架将资源争用和权重摆放视为一等因素，但仍需在商用异构服务器上验证。
EDA & Verification
EDA与验证
Z. Yang, W. Fang, C. Chen, et al.
arXiv:2607.27259 · 2026-07-29
CircuitProver translates parameterized hardware and natural-language specifications into Lean 4 models, then uses an agentic loop to construct machine-checked proofs. Its key proposal is to retain proof traces and theorems as reusable libraries instead of re-solving each design instance with opaque model checking. The idea could lower repeated formal-verification effort, but its value will depend on translation fidelity and performance on industrial-scale RTL.
CircuitProver将参数化硬件和自然语言规格转换为Lean 4模型，再通过代理式循环构造机器检查证明。其核心主张是把证明轨迹和定理沉淀为可复用库，而不是以不透明模型检查为每个设计实例重新求解。这一思路可能降低重复形式验证工作量，但其价值将取决于转换保真度及其在工业级RTL上的性能。
Q. Wu, T. Jafri, A. Arora, V. A. Chhabria
arXiv:2607.24998 · 2026-07-27
VPR-Evolve uses LLM agents to modify the source code of the VPR FPGA place-and-route flow for each target design, scoring candidates through full builds and runs. Across five VTR-9 benchmarks, it improves a composite delay, wirelength, and runtime score by up to 2.7% over stock VPR. The measured gain is modest, yet the work tests a more consequential premise: agents can search beyond conventional CAD hyperparameters if evaluation remains rigorous.
VPR-Evolve使用LLM智能体为每个目标设计修改VPR FPGA布局布线流程的源代码，并通过完整编译和运行来评估候选方案。在五个VTR-9基准上，其延迟、线长和运行时间的综合评分相对原版VPR最高提升2.7%。测得增益并不大，但该工作检验了一个更重要的前提：只要评估足够严格，智能体可以探索超越传统CAD超参数调优的空间。