Circuits & Reliability
电路与可靠性
Haocong Luo, Longda Zhou, et al.
arXiv:2607.28233 · 2026-07-30
This work examines where device-level explanations of RowHammer and RowPress disagree with observed DRAM bit-flip behavior. By focusing on flip direction, flip count, and aggressor-row requirements, it aims to give future characterization and mitigation work a more consistent physical basis rather than relying only on empirical rules.
该工作检视了RowHammer和RowPress的器件级解释与实际DRAM位翻转行为之间的差异。论文聚焦翻转方向、翻转数量和攻击行需求，力图为后续表征与缓解提供更一致的物理基础，而不只依赖经验规则。
Robert S. Aviles, Ziyu Liu, et al.
arXiv:2607.23761 · 2026-07-26
The paper recasts AQFP buffer and splitter insertion as minimizing the width-depth product, a metric intended to track physical-design area better than cell count or logic depth alone. It proves the formulation NP-complete and proposes scalable heuristics, addressing a practical layout bottleneck in superconducting AQFP circuits with explicit fanout and pipeline constraints.
论文将AQFP缓冲器与分路器插入重构为最小化宽度与深度乘积，该指标旨在比单纯的单元数或逻辑深度更好地反映物理设计面积。作者证明该问题为NP完全，并提出可扩展启发式方法，以解决具有显式扇出和流水约束的超导AQFP电路的版图瓶颈。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Sangjin Kim, Yuseon Choi, et al.
arXiv:2607.27704 · 2026-07-30
LightRot combines grouped local rotation and outlier-direction alignment with a hierarchical fast-Hadamard-transform rotation unit for low-bit LLM inference. In a 28 nm CMOS implementation, the authors report 27.4 TOPS/W peak efficiency for 4-bit inference, while the result still depends on the modeled accelerator and the selected LLaMA evaluation workloads.
LightRot将分组局部旋转与离群方向对齐结合，并采用分层快速Hadamard变换旋转单元支持低比特LLM推理。作者在28 nm CMOS实现中报告4比特推理峰值能效为27.4 TOPS/W，但结果仍取决于建模的加速器及所选LLaMA评测负载。
Sookyung Choi, Seungyong Lee, et al.
arXiv:2607.26633 · 2026-07-29
NELSSA routes short-context LLM requests to GPUs and long-context requests to processing-near-memory devices, with migration when a context grows. Its prototype combines PNM sparse attention, GPU decode kernels, and a CXL-enabled runtime, making it a systems proposal for the mixed request lengths that reduce GPU-only batch efficiency.
NELSSA将短上下文LLM请求路由至GPU，将长上下文请求路由至近存处理PNM设备，并在上下文增长时进行迁移。其原型结合PNM稀疏注意力、GPU解码内核和支持CXL的运行时，旨在处理会削弱纯GPU批处理效率的混合请求长度。
Ming-Yen Lee, Hanchen Yang, et al.
arXiv:2607.26491 · 2026-07-29
LLMET is a cross-layer simulation framework for examining how monolithic-3D cache memories change LLM-serving energy. The study reports that expanding L2 from 40 MB to 1 GB reduces chip energy by 44% for Llama 3.1 70B prefill with a 16K context, a promising modeled result that requires realizable M3D memory integration.
LLMET是一套跨层仿真框架，用于考察单片三维缓存如何改变LLM服务的能耗。研究报告称，在16K上下文的Llama 3.1 70B预填充阶段，将L2从40 MB扩展至1 GB可使芯片能耗降低44%；这是有前景的建模结果，但仍依赖可实现的M3D存储集成。
Solomon Micheal Serunjogi, Rachmad Vidya Wicaksana Putra, et al.
arXiv:2607.26016 · 2026-07-28
MDTransformer proposes a photonic transformer co-design that uses spatial modes as independent compute lanes, avoiding multi-wavelength generation and spectral filtering. Its inverse-designed coherent crossbar and IQ modulation target complex matrix operations in the optical domain, but practical value will depend on end-to-end optical packaging, calibration, and electronic I/O overheads.
MDTransformer提出一种光子Transformer协同设计，将空间模式作为独立计算通道，从而避免多波长光源和频谱滤波。其逆向设计的相干交叉阵列与IQ调制瞄准光域复数矩阵运算，但实际价值仍取决于端到端光封装、校准以及电子I/O开销。
Yuan He, Masaaki Kondo, et al.
arXiv:2607.24196 · 2026-07-27
PIMID presents an execution- and trace-driven full-system simulator for processing-in-memory designs. It spans shared-memory and message-passing execution, eleven memory technologies, and placements from subarrays to logic dies, addressing the blind spots of device-only PIM models while still depending on the quality of its component assumptions.
PIMID提出一套面向存内计算设计、由执行与轨迹驱动的全系统仿真器。它覆盖共享内存和消息传递执行模型、11种存储技术，以及从子阵列到逻辑裸片的处理单元放置，弥补仅器件级PIM模型的盲点，但仍依赖各组件假设的准确性。
EDA & Design Automation
EDA与设计自动化
Stef Cuyckens, Mihaela Jivanescu, et al.
arXiv:2607.27879 · 2026-07-30
ARES adapts an LLM agent's reasoning effort during RTL optimization, escalating only after lower-effort iterations stall, and reports normalized dollar cost alongside PPA outcomes. On three unseen test designs, the authors report a 23–27% figure-of-merit reduction versus 16–23% for the best fixed effort, although the training and evaluation set is small.
ARES在RTL优化过程中自适应调整LLM代理的推理强度，仅在低强度迭代停滞后升级，并将标准化美元成本与PPA结果一同报告。作者在三个未见测试设计上报告，FoM降低23–27%，而最佳固定强度为16–23%；但训练和评测集规模较小。
Andrija Nešković, Christian Ewert, et al.
arXiv:2607.23218 · 2026-07-25
SPARC automates pre-silicon detection and root-cause analysis of processor power side-channel leakage using macro-cell information-flow tracking and enhanced shadow logic. It attributes secret-dependent switching to hardware signals and corresponding software instructions, which could make mitigation more actionable than a leakage score alone; validation is reported on open-source RISC-V CPUs.
SPARC利用宏单元级信息流跟踪和增强影子逻辑，自动检测并根因分析处理器流片前功耗侧信道泄漏。它将秘密相关开关活动归因到硬件信号及相应软件指令，因此比单独给出泄漏分数更有助于缓解；验证对象为开源RISC-V CPU。