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Research digest · Wednesday, July 29, 2026 研究摘要 · 2026年7月29日 星期三

Hardware-Aware AI Reaches the System Stack 硬件感知AI走向系统全栈

This week’s work pushes model and system optimization into memory arrays, routing, inference dispatch, and verification. The strongest claims pair algorithmic changes with concrete hardware constraints or measured execution results. 本周研究将模型与系统优化推进到存储阵列、布线、推理调度和验证等环节。较有价值的工作将算法改动与明确的硬件约束或实测执行结果结合起来。

Look-back window: 7 days · 6 paper(s) 回溯窗口: 7天 · 6篇

AI Accelerators & Compute-in-Memory AI加速器与存算一体

Multi-Primitive In-Memory Computing for Monte Carlo Tree Search 用于蒙特卡洛树搜索的多原语存内计算

T. Molom-Ochir, B. F. Morris, et al.

arXiv:2607.22869 · 2026-07-24T19:17:37Z

The paper maps the phases of Monte Carlo tree search to separate in-memory primitives, including CAM, logic, RRAM crossbars, and SRAM, rather than treating the irregular algorithm as a single crossbar workload. Using 22 nm estimates calibrated with fabricated RRAM-array parameters, it reports about 60 mW for 9×9 Go and 96× CPU energy efficiency. The claim is compelling because it tackles an irregular search algorithm, but the end-to-end system is still an architecture evaluation rather than measured silicon. 论文将蒙特卡洛树搜索的各阶段分别映射到CAM、逻辑、RRAM交叉阵列和SRAM等存内原语,而不是把这类不规则算法视为单一交叉阵列工作负载。基于采用已制备RRAM阵列参数校准的22 nm估算,其对9×9围棋报告约60 mW功耗和相对CPU 96倍的能效。该工作的重要性在于处理了不规则搜索算法,但端到端系统仍属架构评估而非实测芯片。

Distribution-Aware MoE Inference with Adaptive Kernel Dispatch 采用自适应核调度的分布感知MoE推理

E.-M. Huang, A.-C. Chang, et al.

arXiv:2607.23099 · 2026-07-25T08:20:47Z

DA-MoE chooses fused-MoE GPU kernels from the live expert-routing histogram instead of only from token-count buckets. On HumanEval-X serving traces, the authors report geometric-mean latency gains of 1.16× for DeepSeek-V3 and 1.29× for Kimi K2, with peaks of 1.40× and 1.56×. It identifies routing skew as a first-class systems variable, although the benefit depends on representative offline tuning and the serving mix matching those distributions. DA-MoE根据实时专家路由直方图选择融合MoE GPU内核,而非仅依据token数量分桶。在HumanEval-X服务轨迹上,作者报告DeepSeek-V3的几何平均延迟改善为1.16倍、Kimi K2为1.29倍,峰值分别达1.40倍和1.56倍。该工作将路由偏斜提升为一等系统变量,但收益依赖有代表性的离线调优及实际服务负载与这些分布的匹配度。

FusionML: CPU+GPU Co-Execution on Unified-Memory Apple Silicon FusionML:统一内存Apple Silicon上的CPU+GPU协同执行

O. Mohite

arXiv:2607.22785 · 2026-07-24T11:42:17Z

FusionML shows that MLX lazy-graph scheduling can serialize CPU–GPU work unless an eager materialization boundary is inserted, then uses contention-aware row splitting for transformer prefill. Across five Apple chips, it reports 1.15–1.38× faster decoder-block prefill and 1.18–1.25× faster time to first token for Qwen2.5-7B, with unchanged decode throughput. The useful result is that shared memory alone does not guarantee operator-level parallelism. FusionML指出,若不插入即时物化边界,MLX的惰性图调度会将CPU-GPU工作串行化;随后它为Transformer prefill采用了考虑争用的行切分。在五款Apple芯片上,作者报告解码器块prefill加速1.15至1.38倍,Qwen2.5-7B的首token时间加速1.18至1.25倍,而decode吞吐不变。其关键结论是:统一内存本身并不保证算子级并行。

Devices & Process 器件与工艺

Magnetic Tunnel Junctions for Timekeeping in Intermittent Systems 利用磁隧道结实现间歇计算系统计时

N. V. Maruszewski, J. Athas, et al.

arXiv:2607.23000 · 2026-07-25T02:28:23Z

FLINT uses deliberately stochastic retention loss in magnetic tunnel junctions to estimate off-time in batteryless intermittent systems, avoiding capacitor-discharge timing. A model validated against 21 fabricated MTJs reports 15 minutes of off-time within 10% error at 1.03 μJ and under 0.1 mm². The result points to a useful nonvolatile timing primitive, though system performance beyond the device-trace-driven evaluation remains to be demonstrated in hardware. FLINT利用磁隧道结中可预测的随机保持失效来估计无电池间歇系统的断电时间,从而避免采用电容放电计时。以21个已制备MTJ验证的模型报告,在1.03 μJ和不足0.1 mm²条件下,可在15分钟断电时间内实现10%以内误差。该结果提出了一种有潜力的非易失计时原语,但设备轨迹驱动评估之外的完整硬件系统性能仍待验证。

EDA & Design Verification EDA与设计验证

DRC-Aid: Verification-in-the-Loop Design-Rule Repair DRC-Aid:验证闭环的设计规则修复

A. Mukherjee, K. He, K. Roy

arXiv:2607.22761 · 2026-07-23T21:22:36Z

DRC-Aid limits an LLM to choose among rule-engine-generated geometric edits and immediately verifies each choice with physical-design tools. On FreePDK45 layouts, it reports DRC-clean, LVS-equivalent repair in about 92.5% of cases and a 98% reduction in total violations. Its strongest choice is constraining the model with deterministic edits and verification, though the evaluation is on an academic process kit rather than production designs. DRC-Aid将LLM限制为从规则引擎生成的几何编辑中进行选择,并用物理设计工具立即验证每次选择。在FreePDK45版图上,它报告约92.5%的案例可实现DRC清洁且LVS等价的修复,总违规数减少98%。其最强之处是用确定性编辑和验证约束模型,但评估基于学术工艺库而非量产设计。

Quantum Computing 量子计算

ARGON: GNN-Guided Compilation for Neutral-Atom Computing ARGON:面向中性原子计算的GNN引导编译框架

W. Sun, X. Li, et al.

arXiv:2607.21216 · 2026-07-23T11:30:05Z

ARGON separates neutral-atom compilation into an offline library of hardware-certified spatial layouts and a GNN-guided temporal-routing stage. The approach is intended to avoid movement and conflict bottlenecks as circuits grow while preserving highly parallel entangling operations. It is a practical compiler direction for dynamic-atom hardware, but its value will depend on how well the precomputed layout library captures changing device constraints and error behavior. ARGON将中性原子编译拆分为离线构建的硬件认证空间布局库,以及由GNN引导的时间路由阶段。该方法旨在随着电路规模增长时规避原子移动和冲突瓶颈,同时保留高度并行的纠缠操作。这是面向动态原子硬件的务实编译方向,但其价值取决于预计算布局库对不断变化的器件约束和误差行为的覆盖程度。

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