Circuits, Architecture & Reliability
电路、架构与可靠性
C. Liu, Y. Chen, T. E. Carlson
arXiv:2607.19922 · 2026-07-22T08:53:09Z
DGNA measures L2-cache and DRAM latency without architecture-specific intrinsic instructions, then uses a Gaussian mixture model to separate latency distributions from outliers. The authors apply the method to Nvidia A100 and H100 GPUs, offering software and simulator designers a way to infer otherwise undocumented NUMA behavior. These are reverse-engineered microbenchmark results, not vendor-confirmed topology.
DGNA无需依赖特定架构的内建指令即可测量L2缓存与DRAM延迟，并使用高斯混合模型从异常值中分离延迟分布。作者将该方法用于Nvidia A100与H100 GPU，为软件和模拟器设计者推断未公开的NUMA行为提供路径。这些结论来自逆向微基准，并非厂商确认的拓扑。
P. Metku, C. Gandu
arXiv:2607.20141 · 2026-07-22T13:43:43Z
This work recasts chiplet screening as a Bayesian inference problem that maps pre-assembly telemetry to post-assembly failure risk, with safety gates and uncertainty-aware disposition boundaries. The framework addresses a real gap: a functionally good die is not automatically a die with a quantified lifetime guarantee after packaging. Validation uses Monte Carlo data from 4,000 synthetic dies, so fab telemetry and field failures are still needed to test calibration.
该研究把chiplet筛选重构为贝叶斯推断问题，将封装前遥测数据映射为封装后失效风险，并加入安全门控与不确定性感知的处置边界。它直指一个现实缺口：功能合格的裸片并不自动具备封装后的量化寿命保证。验证仅使用4,000颗合成裸片的蒙特卡洛数据，仍需晶圆厂遥测与现场失效数据检验其校准能力。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
H. Ding, L. Liang, R. Qiao, et al.
arXiv:2607.22022 · 2026-07-24T06:40:36Z
HEMERA algebraically reformulates Mamba-2's matrix-form state-space duality into a streaming-recursive dataflow that avoids quadratic intermediate materialization. A heterogeneous memory-centric accelerator then maps state propagation and matrix work onto different execution resources, directly targeting edge bandwidth limits. The supplied preprint record does not include complete benchmark or measured-silicon figures, so the claimed system advantage remains to be quantified independently.
HEMERA把Mamba-2矩阵形式的状态空间对偶计算代数重构为流式递归数据流，从而避免二次方规模的中间结果物化。异构内存中心加速器再将状态传播与矩阵运算映射到不同执行资源，直接瞄准边缘设备的带宽限制。所给预印本记录未包含完整基准或实测芯片数据，其系统优势仍需独立量化。
G. Narang, A. R. Bommana, K. Chakrabarty
ACM Transactions on Design Automation of Electronic Systems · 2026-07-22
PHONON jointly optimizes compute-to-compute and compute-to-storage traffic in a silicon-photonic network on an interposer for multi-chiplet LLM inference. Structured waveguide placement, cluster-level storage connectivity, and kernel mapping aim to reduce crossings, propagation loss, and long multi-hop transfers. The paper targets a credible packaging bottleneck, but the supplied record does not show a fabricated photonic interposer, so its gains should be read as architectural evidence.
PHONON面向多chiplet LLM推理，在硅光中介层网络中协同优化计算到计算与计算到存储的流量。其结构化波导布局、簇级存储连接和计算核映射旨在减少交叉、传播损耗及长距离多跳传输。论文瞄准了可信的封装瓶颈，但所给记录未显示已制造的光子中介层，因此相关收益应视为架构层证据。
C. E. Song, S. Pinge, T. Zhang, et al.
arXiv:2607.17538 · 2026-07-20T04:31:09Z
D-NOVA embeds an IVF-based retrieval pipeline into the 3D NAND array using a NAND-tailored dual-bound similarity metric and a lightweight vector adapter. The design attacks the nearly 70% of retrieval time that the paper attributes to processors outside storage, potentially reducing movement in RAG serving. The candidate record does not provide measured-array results, leaving sensing margins, endurance, and recall under device variation as open questions.
D-NOVA利用面向NAND的双界相似度指标与轻量向量适配器，把基于IVF的检索流程嵌入3D NAND阵列。该设计针对论文所称近70%的检索时间消耗在存储器外处理器上的问题，有望减少RAG服务中的数据搬运。候选记录未提供阵列实测结果，感测裕量、耐久性及器件波动下的召回率仍是开放问题。
Hardware-Relevant AI Research
硬件相关AI研究
C. Fang, J. Yin, M. Shi, et al.
arXiv:2607.22389 · 2026-07-24T15:15:10Z
HiKV first evicts low-importance tokens and then loads only significant elements within retained tokens, with one reconfigurable sorter accelerating both stages. Across representative LLMs, the authors report up to 7.95x attention speedup, 90% lower energy, and no more than 1% accuracy loss; at equal accuracy, external-memory accesses fall another 1.82–4.87x versus prior importance-based methods. The results are from a preprint and still need independent reproduction on deployed hardware.
HiKV先淘汰低重要性Token，再仅加载保留Token中的关键元素，并用一个可重构排序器加速两个阶段。作者在代表性LLM上报告最高7.95倍注意力加速、90%能耗降低且精度损失不超过1%；在等精度条件下，外部内存访问较既有重要性感知方法进一步减少1.82至4.87倍。该结果来自预印本，仍需在实际部署硬件上独立复现。
F. Waschkowski, P. Rathnayaka, L. Wesemann
arXiv:2607.19438 · 2026-07-21T06:42:18Z
BaseRT adds hand-written Metal 4 kernels for dense and MoE GEMM plus flash-attention prefill, routing compute-bound work through the M5's per-core Neural Accelerators while retaining specialized decode kernels. On an M5 Pro across 15 model configurations up to 35B parameters, it reports as much as 6.4x higher prompt throughput than llama.cpp, 3.9x over MLX, and up to 1.75x faster decode than llama.cpp. The comparison is platform-specific, and broader reproducibility will depend on public code and matched quantization settings.
BaseRT为稠密与MoE GEMM以及Flash Attention预填充加入手写Metal 4内核，把计算受限任务送入M5每个核心的Neural Accelerator，同时保留专用解码内核。在M5 Pro上测试15种、最高35B参数的模型配置后，论文报告提示词处理吞吐最高为llama.cpp的6.4倍、MLX的3.9倍，解码速度最高比llama.cpp快1.75倍。该比较高度依赖平台，更广泛的可复现性取决于公开代码与一致的量化设置。
H. Jang, I. Song, S. H. Noh, et al.
arXiv:2607.18141 · 2026-07-20
HyMCache combines a small in-device DRAM tier with SSD-backed capacity behind CXL to store reusable KV state for long-context, multi-turn serving. Request-level prefix prefetching and opportunistic write buffering exploit the cache's predictable, read-heavy, append-only behavior, aiming for TB-scale capacity at SSD cost. Evaluation uses a real CXL-hybrid-memory prototype, but the supplied record omits the final comparative numbers, so latency under larger shared workloads remains the key result to inspect.
HyMCache把少量设备内DRAM与CXL接口后的SSD容量结合，用于存储长上下文、多轮服务中可复用的KV状态。请求级前缀预取与机会式写缓冲利用KV Cache可预测、读密集和仅追加的访问特征，目标是在SSD成本下提供TB级容量。评估使用真实CXL混合内存原型，但所给记录缺少最终对比数字，因此更大规模共享负载下的延迟仍是最值得核查的结果。