Devices & Process
器件与工艺
P. Su, J. Chen, J. Li, et al.
Science Advances · 2026-07-03
Su et al. stabilize a ferrielectric phase inside low-temperature PbZrO3 thin films, creating a triple-hysteresis loop rather than the usual ferroelectric or antiferroelectric response. The reported electrocaloric temperature change reaches -23.76 K by Maxwell-relation extraction, about a 600% enhancement versus the double-hysteresis baseline in the abstract. The result is interesting for solid-state cooling and multistate memory, but the cooling number is still an inferred device metric rather than a packaged thermal system.
Su等人在低温制备的PbZrO3薄膜中稳定出铁电相，在常见铁电或反铁电响应之外形成三重滞回回线。摘要给出的基于Maxwell关系提取的电热温变达到-23.76 K，较双重滞回基线提升约600%。该结果对固态制冷和多态存储有吸引力，但这个制冷指标仍是器件层面推导值，而不是封装热系统实测。
Z. Chen, T. Hu, X. Jia, et al.
IEEE Transactions on Electron Devices · 2026-07-01
Chen et al. insert Al2O3 layers as both tunneling dielectric and gate interlayer in an HfZrO2 FeFET stack. With a 2 nm tunneling layer and 3 nm gate interlayer, the devices show a 9 V memory window and projected 0.44% memory-window loss over 10 years at -13 V to +14 V operation. The retention result is strong for FeFET scaling discussions, but the operating voltage and stack complexity remain important manufacturability questions.
Chen等人在HfZrO2 FeFET栈中引入Al2O3，同时作为隧穿介质层和栅介质插层。在2 nm隧穿层与3 nm栅插层条件下，器件显示9 V存储窗口，并在-13 V至+14 V工作下预测10年存储窗口损失仅0.44%。这一保持特性对FeFET缩放很有参考价值，但工作电压和堆栈复杂度仍是制造可行性的关键问题。
X. Zhou, G. Zhou, Y. Lv, et al.
IEEE Transactions on Electron Devices · 2026-07-01
Zhou et al. fabricate AlGaN/GaN HEMTs on polycrystalline diamond using room-temperature wafer bonding and a roughly 17 nm bonding interface. Load-pull measurements on 4 x 100 micron devices report 25.28 W/mm at 10 GHz with 33.43% power-added efficiency, while channel temperature falls by about 150 C versus GaN-on-SiC at 31.5 W/mm DC power density. The paper attacks the RF power thermal wall directly; the next question is whether the bonding interface can scale with yield and cost.
Zhou等人通过室温晶圆键合和约17 nm键合界面，在多晶金刚石衬底上制备AlGaN/GaN HEMT。4 x 100微米器件的负载牵引测试在10 GHz下达到25.28 W/mm，功率附加效率为33.43%，并且在31.5 W/mm直流功率密度下相比GaN-on-SiC沟道温度降低约150 C。论文直接针对RF功率器件的热墙；下一步问题是该键合界面能否以可接受良率和成本放大。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
L. Pei, J. Zheng, X. Zhao, et al.
arXiv:2607.02465 · 2026-07-02T17:31:17Z
Pei et al. propose p-MEM, a memory primitive that stores distribution parameters and samples directly at memory bandwidth instead of generating Gaussian random numbers as a separate compute step. The layout-validated simulator reports more than 1000 GSa/s/mm2 GRNG throughput, plus CPU/GPU reductions of up to 2.19x/4.37x in instruction count, 562x/3.45x in sampling latency, and 295.5x/3.53x in energy for Bayesian neural-network workloads. This is a hardware-relevant answer to probabilistic AI overhead, but it remains a simulated architecture rather than measured silicon.
Pei等人提出p-MEM，一种存储分布参数并直接以存储带宽采样的存储原语，而不是把高斯随机数生成作为独立计算步骤。经过版图验证的模拟器显示，GRNG吞吐超过1000 GSa/s/mm2，并在贝叶斯神经网络负载中让CPU/GPU指令数最多降低2.19x/4.37x，采样延迟降低562x/3.45x，能耗降低295.5x/3.53x。这是对概率AI开销的硬件化回应，但目前仍是模拟架构而非实测硅片。
Z. Qian, Z. Cong, S. Yan, et al.
IEEE Journal of Solid-State Circuits · 2026-07-01
Qian et al. present a 28 nm compute-in-memory chip that pulls system-level components, except control logic, into a single macro. The design uses leakage-eliminated 2T1C and capacitor-over-logic 1T1C eDRAM to reduce the SRAM access, long interconnect, and accumulation overheads that often erase macro-level CIM gains. The paper is valuable because it treats CIM as a system layout problem, not only as a bitcell energy-efficiency claim.
Qian等人展示了一颗28 nm存内计算芯片，把除控制逻辑外的系统级组件整合进单个宏单元。该设计采用消除漏电的2T1C和电容置于逻辑之上的1T1C eDRAM，以减少SRAM访问、长互连和累加单元开销，这些开销常常抵消宏单元层面的CIM收益。论文的价值在于把CIM视为系统版图问题，而不只是位单元能效声明。
Y. Jiang, X. Wang, H. You, et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2026-07-01
Jiang et al. build a Booth-based all-digital SRAM CIM macro for flexible multiply-accumulate operations across bit widths. The 55 nm CMOS measurement reports 16.8 TOPS/W for 8b/8b MACs, using pre-encoding, two-transistor bit retention and shifting, and multiphase accumulation to reduce overhead. It is a practical digital-CIM entry because the result keeps standard CMOS and integer precision in view, though array-scale integration details still determine system usefulness.
Jiang等人构建了一个基于Booth编码的全数字SRAM CIM宏，用于支持不同位宽的乘加运算。55 nm CMOS实测在8b/8b MAC下达到16.8 TOPS/W，并通过预编码、两晶体管位保持与移位、多相累加来降低开销。这是一个更偏实用的数字CIM结果，因为它保留了标准CMOS和整数精度视角，但系统价值仍取决于阵列级集成细节。
M. Usman, S. Khan, D. Merhof
arXiv:2607.01798 · 2026-07-02T07:15:08Z
Usman et al. replace the costly softmax exponential in FPGA Vision Transformer inference with a 16-segment piecewise-linear natural-exponential approximation implemented in distributed LUT fabric. On a Xilinx Zynq-7020 attention-row core, the design uses 1444 LUTs, 77 DSPs, and no BRAM, avoiding table-heavy or CORDIC-style implementations. The hardware angle is clear for small FPGAs, but the reported result is still core-level and depends on model-level accuracy under approximation.
Usman等人用16段分段线性自然指数近似替代FPGA视觉Transformer推理中昂贵的softmax指数计算，并完全用分布式LUT织构实现。在Xilinx Zynq-7020的attention-row核心上，该设计使用1444个LUT、77个DSP且不占用BRAM，避免了查表密集或CORDIC式实现。其硬件价值对小型FPGA很明确，但结果仍处于核心级，最终取决于近似下的模型级精度。