Devices & Process
器件与工艺
Zhou-Yu Wu, A. Ramesh, Vinod N. Bhukya, Jeng-Hua Wei, S. Sheu, Y. Hsin, Yuan-Chieh Tseng
IEEE TED DOI:10.1109/TED.2026.3692177 · 2026-07-01
The paper experimentally studies Mg insertion at CoFeB/MgO interfaces in PMA MTJs with diameters from 30 to 180 nm and propagates the measured statistics into CIM array simulations. Mg insertion raises RA, lowers switching current, improves breakdown voltage, and reduces TMR, creating a device-level tradeoff for array read margins and energy. The useful contribution is the closed device-to-array loop rather than another idealized CIM simulation.
这篇论文实验研究了PMA MTJ中CoFeB/MgO界面的Mg插入，器件直径覆盖30到180 nm，并把测得的统计分布传递到CIM阵列仿真中。Mg插入提高RA、降低开关电流、提升击穿电压，但会降低TMR，因此在阵列读裕量和能耗之间形成器件级权衡。它的价值在于建立了从器件到阵列的闭环，而不是又一次理想化的CIM仿真。
Jiawei Xie, Zuopu Zhou, Leming Jiao, Yuye Kang, Kaizhen Han, Zijie Zheng, Qiwen Kong, Xiaolin Wang, Bich-Yen Nguyen, Xiao-Qing Gong
IEEE TED DOI:10.1109/TED.2026.3692625 · 2026-07-01
The authors demonstrate a BEOL-compatible nonvolatile SRAM cell using HfO2-based MFM ferroelectric capacitors and ITO-channel FETs. The process stays at or below 400 C, supports store and recall, and operates with 1.5 V VDD plus a 2 V plate-line voltage in the reported cell. The result is relevant for monolithic 3D memory above CMOS, though density and endurance still need full product-level validation.
作者展示了BEOL兼容的非易失SRAM单元，采用HfO2基MFM铁电电容和ITO沟道FET。该工艺最高温度不超过400 C，已演示store和recall操作，报告单元使用1.5 V VDD和2 V plate line电压。这个结果对CMOS上方单片3D存储有意义，但密度和耐久性仍需产品级验证。
H. Kottur, Nusra Akter Takia, Mahamudul Hassan Fuad, I. Shiam, M. Walsh, Navid Asadizanjani
arXiv:2606.22149 · 2026-06-20
This survey collects roughly 100 industry responses on failure analysis for chiplets, heterogeneous integration, hybrid bonding, and buried package structures. Heterogeneous, chiplet, and 3D products dominate the respondent base at 69%, while package and heterogeneous-integration failure analysis gets a 7.92 out of 10 importance rating. Hybrid bonding is identified as the hardest new architecture to analyze at 54%, and 83% of respondents support formal data standardization.
这项调查收集了约100份行业反馈，聚焦chiplet、异构集成、混合键合和埋入式封装结构的失效分析。异构、chiplet和3D产品占受访基础的69%，封装与异构集成失效分析的重要性评分达到7.92/10。混合键合被54%的受访者认为是最难分析的新架构，同时83%的受访者支持正式的数据标准化框架。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Bing Wu, Xueliang Wei, Shiyi Song, Yibo Liu, Jinpeng Liu, Wei Tong, Hao Tong, Yuchong Hu, Dan Feng
arXiv:2606.31554 · 2026-06-30T12:11:26Z
PATH reformulates hash-index insert, search, update, and delete operations as massively parallel content-addressable operations inside memristive memory arrays. On the authors' workloads it reports 4.7 to 7.8 times higher throughput, more than 14.5 times lower tail latency, and over 61.4% fewer memory accesses for insertions. The caveat is that system value depends on realistic CAM array costs and integration, but the indexing focus is more concrete than generic PIM claims.
PATH把哈希索引的插入、搜索、更新和删除改写为忆阻存储阵列内部的大规模并行内容寻址操作。在作者的工作负载上，它报告了4.7到7.8倍吞吐提升、超过14.5倍尾延迟降低，以及插入场景中超过61.4%的访存减少。需要注意的是，系统价值仍取决于真实CAM阵列成本和集成难度，但把目标放在索引上比泛泛讨论PIM更具体。
Yilong Zhao, Fangxin Liu, Onur Mutlu, Mingyu Gao, Jian Liu, Haibing Guan, Li Jiang
arXiv:2606.30553 · 2026-06-29T16:49:17Z
COSM targets on-device LLM and application workloads where CPU tasks and PIM operations must share constrained mobile DRAM resources. The framework adds a low-interference PIM control interface and schedules PIM commands into idle windows in the CPU memory-access stream. The paper is useful because it treats bank conflicts and bus congestion as first-order issues rather than assuming PIM runs in isolation.
COSM面向端侧LLM和应用负载，在这类场景中CPU任务与PIM操作必须共享受限的移动DRAM资源。该框架加入低干扰PIM控制接口，并把PIM命令调度进CPU访存流的空闲窗口。论文的价值在于把bank冲突和总线拥塞作为一等问题处理，而不是假设PIM可以孤立运行。
Rick Luiken, Manil Dev Gomony, Sander Stuijk
arXiv:2606.30039 · 2026-06-29T09:35:42Z
Mega is a fabricated 22 nm FDSOI accelerator for convolutional spiking neural networks. It combines parallel 3 by 3 convolution support, unified memory for spikes, neuron states, and weights, and low-overhead spike-map handling. The reported 0.375 pJ/SOP is a 4 times improvement over prior state of the art, making this one of the stronger measured-silicon results in the week's accelerator set.
Mega是一款已流片的22 nm FDSOI卷积脉冲神经网络加速器。它结合了并行3乘3卷积、用于spike、神经元状态和权重的统一存储，以及低开销spike map处理。论文报告0.375 pJ/SOP能效，相比此前先进水平提升4倍，是本周加速器论文中较强的实测硅结果。
EDA & Co-Design
EDA与协同设计
Baiyu Chen, Lin Gan, Guangwen Yang, Wenjian Yu
arXiv:2606.31535 · 2026-06-30T11:50:46Z
PEERS attacks effective-resistance computation, a bottleneck in power-grid analysis, spectral sparsification, and reliability sign-off. It uses an implicit inverse model of the Cholesky factor plus augmented symbolic analysis to avoid the usual precision-memory tradeoff in exact methods. The contribution is relevant because industrial sign-off often cannot accept approximate answers, but exact all-edge queries can otherwise explode in memory.
PEERS面向有效电阻计算这一瓶颈，该问题出现在电源网格分析、谱稀疏化和可靠性签核中。它使用Cholesky因子的隐式逆模型和增强符号分析，避免精确方法常见的精度与内存权衡。其意义在于，工业签核往往不能接受近似答案，但精确的全边查询又容易导致内存爆炸。
Yang Zou, Zijian Ding, Yizhou Sun, Jason Cong
arXiv:2606.30949 · 2026-06-29T22:02:34Z
AgRefactor uses an LLM-based multi-agent workflow to convert real-world software into HLS-compatible programs. It adds a self-evolving memory system and combines LLM rewrites with automated refactoring tools to reduce cost and improve robustness. On 9 of 11 longer real-world benchmarks, it matches or beats prior automated and LLM-based baselines, but the result should still be read as a workflow advance rather than a replacement for hardware-aware engineering review.
AgRefactor使用基于LLM的多智能体流程，将真实软件重构为兼容HLS的程序。它加入自演化记忆系统，并把LLM改写与自动化重构工具结合，以降低成本并提升鲁棒性。在11个更长的真实基准中，它在9个上追平或超过既有自动化和LLM基线，但这个结果更应被看作工作流进展，而不是替代硬件感知工程审查。