Hardware Workloads Move Closer to the Metal 硬件工作负载贴近底层

This week’s papers emphasize measurement and co-design: Blackwell video encoders, phone NPUs, real-time RISC-V cores, chiplet placement, and EDA agents all move beyond abstract models. Several results are still simulation-heavy, but the useful thread is the same: software decisions are being pulled into hardware constraints earlier. 本周论文强调测量与协同设计：Blackwell视频编码器、手机NPU、实时RISC-V核心、chiplet布局和EDA agent都在从抽象模型走向更贴近硬件的评估。部分结果仍偏仿真，但有价值的主线一致：软件决策正在更早地受到硬件约束牵引。

Look-back window: 7 days · 10 paper(s) 回溯窗口: 7天 · 10篇

Devices & Process 器件与工艺

NEMS primitives for hardware security in advanced packaging 面向先进封装硬件安全的NEMS原语

H. R. Kottur, P. Arjunamahanthi, M. S. M. Khan, et al.

arXiv:2606.26426 · 2026-06-24T22:33:33Z

Kottur et al. frame nanoelectromechanical systems as physical security primitives for advanced packaging, including PUFs, resonance fingerprints, shape-memory materials, and physical unlocking mechanisms. The useful angle is that packaging security needs device-level assurance, not only digital cryptographic wrappers. The paper reads as a technology-mapping proposal rather than a measured manufacturing result, so the next proof point is integration data in a standard semiconductor flow. Kottur等人将纳机电系统（NEMS）定义为先进封装中的物理安全原语，包括PUF、谐振指纹、形状记忆材料和物理解锁机制。它的有价值之处在于指出封装安全需要器件级保证，而不只是数字密码学外壳。这篇论文更像技术路线映射，而不是已验证的制造结果，下一步需要在标准半导体流程中的集成数据。

Circuits & Architecture 电路与架构

SHIFT relocates compute in communication-aware chiplet systems SHIFT在通信感知chiplet系统中迁移计算

A. Delavari, L. Popryho, I. Partin-Vaisband, et al.

arXiv:2606.28754 · 2026-06-27T06:02:23Z

Delavari et al. propose SHIFT, a topology-agnostic runtime method that moves compute context toward a better-positioned node instead of only routing data around a chiplet fabric. The design uses utility chiplets, multi-layer routing, a modified shortest-path algorithm, and a lightweight ML policy for traffic adaptivity. The paper is simulation-oriented, but it targets a real scaling issue: chiplet systems increasingly pay for data motion more than arithmetic. Delavari等人提出SHIFT，这是一种拓扑无关的运行时方法，不只是把数据绕过chiplet互连，而是将计算上下文迁移到位置更合适的节点。该设计使用utility chiplet、多层路由、修改版最短路径算法和轻量ML策略来适应流量变化。论文以仿真为主，但瞄准了真实扩展问题：chiplet系统越来越多地为数据移动而不是算术本身付出代价。

CVA6-RT adds time-predictable real-time features to an open RV64 core CVA6-RT为开放RV64核心加入时间可预测实时特性

E. Zelioli, C. Reinwardt, N. Wistoff, et al.

arXiv:2606.26177 · 2026-06-24T11:52:10Z

Zelioli et al. extend the open-source CVA6 core with TLB partitioning and locking, scratchpad-style L1 cache modes, and low-latency interrupt handling with hardware-assisted context stacking. With real-time features enabled, CVA6-RT reaches 12-cycle interrupt latency, about 10x lower than baseline CVA6 and comparable to simpler Arm Cortex-M microcontrollers. The result is relevant for mixed-criticality systems that want Linux-class RISC-V openness without giving up deterministic response. Zelioli等人为开源CVA6核心加入TLB分区与锁定、可重构scratchpad式L1缓存模式，以及带硬件辅助上下文堆栈的低延迟中断处理。启用实时特性后，CVA6-RT实现12周期中断延迟，比基线CVA6低约10倍，并可与更简单的Arm Cortex-M微控制器相当。这个结果适合希望保留Linux级RISC-V开放性、同时又需要确定性响应的混合关键系统。

Croc turns open-source silicon education into fabricated RISC-V chips Croc将开源硅设计教学推进到已制造RISC-V芯片

E. Zelioli, P. Sauter, T. Benz, et al.

arXiv:2606.25673 · 2026-06-24T10:37:00Z

Zelioli et al. present Croc, an end-to-end open-source RISC-V SoC design and fabrication flow built around open SystemVerilog IP and a 130 nm open PDK. In the first course run, 65 students completed 33 projects, 30 produced manufacturable layouts, 18 were tapeout candidates, and five were fabricated; a baseline chip has already been characterized in silicon. The paper matters less as a leading-node result than as evidence that open flows can teach full-stack chip design with real silicon feedback. Zelioli等人介绍Croc，这是一个围绕开源SystemVerilog IP和130nm开放PDK构建的端到端开源RISC-V SoC设计与制造流程。在首次课程实践中，65名学生完成33个项目，其中30个生成可制造版图，18个成为流片候选，5个完成制造；一个基线芯片已完成硅上表征。它的重要性不在先进制程，而在证明开源流程可以通过真实硅反馈训练完整芯片设计能力。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

Blackwell hardware encoders make high-fidelity V-PCC practical on general GPUs Blackwell硬件编码器让高保真V-PCC可在通用GPU上实现

K. Arunruangsirilert, J. Katto

arXiv:2606.29179 · 2026-06-28T03:54:36Z

Arunruangsirilert and Katto evaluate 8K, 10-bit, 4:2:2 HEVC encoding for video-based point-cloud compression on a commercial Nvidia Blackwell GPU with four on-die hardware encoders. The novelty is not a new codec, but showing that a workload previously pushed toward custom ASICs can move onto general-purpose GPU hardware because Blackwell adds the needed 10-bit 4:2:2 path. The result is workload-specific, but it is a concrete example of fixed-function blocks changing the accelerator boundary. Arunruangsirilert和Katto在一块商用Nvidia Blackwell GPU上评估面向视频点云压缩的8K、10-bit、4:2:2 HEVC编码，该GPU包含4个片上硬件编码器。新意不在新编解码器，而在说明过去偏向定制ASIC的工作负载，因为Blackwell加入所需的10-bit 4:2:2路径，可以转移到通用GPU硬件上。这个结果具有工作负载特定性，但它清楚展示了固定功能模块如何改变加速器边界。

Mobile VLM inference depends sharply on phase and backend placement 移动端VLM推理强烈依赖阶段与后端映射

A. V. Murthy, Y. N. Kotre, P. Sharma, et al.

arXiv:2606.27906 · 2026-06-26T09:54:33Z

Murthy et al. characterize vision-language inference on a Snapdragon 8 Elite-class mobile SoC using hardware-in-the-loop measurements. The NPU gives a 1.64x speedup for prefill but only 1.18x for decode, while vision encoders see 20-45x CPU speedups; the best paths cut steady-state temperature by 10.47 degrees C and energy by 2.52x. The paper is useful because it turns “run it on the NPU” into a phase-by-phase mapping problem for on-device AI. Murthy等人使用硬件在环测量，表征Snapdragon 8 Elite级移动SoC上的视觉语言模型推理。NPU在prefill阶段带来1.64倍加速，但在decode阶段只有1.18倍；视觉编码器相对CPU有20-45倍加速，最佳路径使稳态温度降低10.47摄氏度、能耗降低2.52倍。论文的价值在于把「跑在NPU上」拆解成按阶段映射的移动端AI问题。

MSDF digit-serial arithmetic accelerates U-Net convolution on FPGA MSDF数字串行算术在FPGA上加速U-Net卷积

M. Usman, Y. Sadegheih, D. Merhof

arXiv:2606.25562 · 2026-06-24T08:37:40Z

Usman et al. build an FPGA convolution accelerator for U-Net that uses most-significant-digit-first digit-serial arithmetic and a merged multiply-add pipeline. The merged unit avoids accumulating startup latency from cascaded multiply and add blocks, improving throughput despite lower FPGA clock frequency than a CPU. The work is narrower than a full accelerator SoC, but it is a concrete arithmetic-level optimization for energy-constrained segmentation workloads. Usman等人为U-Net构建FPGA卷积加速器，采用最高有效位优先（MSDF）的数字串行算术和融合乘加流水线。融合单元避免了乘法和加法模块级联时启动延迟不断累积的问题，即便FPGA频率低于CPU，也能提升吞吐。该工作比完整加速器SoC范围更窄，但它是面向能耗受限分割工作负载的具体算术级优化。

AI Research for Hardware 面向硬件的AI研究

KernelSight-LM simulates LLM inference at kernel-level granularity KernelSight-LM以kernel级粒度模拟LLM推理

X. Yao, T. Kim, H. Pei, et al.

arXiv:2606.28565 · 2026-06-26T19:43:38Z

Yao et al. present KernelSight-LM, an LLM inference simulator that decomposes serving into kernel roofline models, learned efficiency terms, communication, host overhead, prefix caching, and continuous batching. In a cross-generation setting with no target-GPU measurements, it predicts per-kernel latency on an unseen GPU generation at 12.1% error, versus 22.0% for a roofline baseline. The simulator is useful for hardware planning because inference bottlenecks are now shaped by serving policy as much as raw FLOPS. Yao等人提出KernelSight-LM，这是一个LLM推理模拟器，将服务过程拆解为kernel roofline模型、学习得到的效率项、通信、主机开销、prefix caching和continuous batching。在没有目标GPU测量数据的跨代设置中，它对未见GPU世代的单kernel延迟预测误差为12.1%，而roofline基线为22.0%。该模拟器对硬件规划有用，因为推理瓶颈如今既受原始FLOPS影响，也受服务策略影响。

EDA & Design Automation EDA与设计自动化

HORIZON treats hardware design as repository-level code evolution HORIZON将硬件设计视为仓库级代码演化

C. Yu, C. Deng, N. Pinckney, et al.

arXiv:2606.28279 · 2026-06-26T17:21:06Z

Yu et al. introduce HORIZON, a self-evolving agent framework that packages hardware-design tasks into repositories with domain knowledge, executable evaluators, acceptance predicates, and git/runtime policy. The system reports 100% benchmark completion across ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories. The authors are explicit that these are controlled proxies, so the result is best read as progress in evaluation harnesses and agent workflow, not proof that autonomous chip design is solved. Yu等人提出HORIZON，这是一个自演化agent框架，把硬件设计任务封装为包含领域知识、可执行评测器、验收条件以及git/运行时策略的代码仓库。系统在ChipBench、RTLLM、Verilog-Eval和9类CVDP任务上报告100%基准完成率。作者明确指出这些仍是受控代理任务，因此应将其理解为评测框架和agent工作流的进展，而不是自主芯片设计已被解决的证明。

Evidence-driven LLM agents repair C into synthesizable HLS code 证据驱动LLM agent将C修复为可综合HLS代码

Z. Zhao, H. Lang, Z. Xiao, et al.

arXiv:2606.28409 · 2026-06-25T02:55:02Z

Zhao et al. cast C-to-HLS-C conversion as a closed-loop generation, verification, diagnosis, and repair problem around Xilinx Vitis. Their workflow uses a four-stage verifier, Progressive Mismatch Localization Chain, AST slicing, dual-trace instrumentation, and a typed evidence RAG system instead of handing raw logs directly to an LLM. The result matters for EDA because HLS productivity depends less on first-shot code generation than on reproducible repair through compile, CSim, synthesis, and CoSim stages. Zhao等人将C到HLS-C转换定义为围绕Xilinx Vitis的生成、验证、诊断和修复闭环问题。其流程使用四阶段验证器、Progressive Mismatch Localization Chain、AST切片、双轨迹插桩和类型化证据RAG系统，而不是直接把原始日志交给LLM。该结果对EDA有意义，因为HLS生产力并不主要取决于一次性生成代码，而取决于能否在编译、CSim、综合和CoSim阶段可复现地修复问题。