Circuits & Architecture
电路与架构
Tamilselvi P., Jeyasudha S., Ranjitha R., Sanmugapriya M., Neethu K., et al.
International Research Journal on Advanced Engineering Hub (IRJAEH) · 2026-06-26
The paper reviews and evaluates approximate ALU techniques for VLSI designs, including truncated computation, speculative addition, and logic simplification. It frames accuracy loss through metrics such as mean error distance and error rate while comparing area, delay, and energy trade-offs. The result is most relevant for error-tolerant workloads such as multimedia, machine learning, and embedded signal processing, where lower switching activity can be worth bounded numerical error.
这篇论文梳理并评估用于VLSI设计的近似ALU技术，包括截断计算、推测加法和逻辑简化。论文用平均误差距离、错误率等指标刻画精度损失，并比较面积、延迟和能耗权衡。其价值主要面向多媒体、机器学习和嵌入式信号处理等可容忍误差的工作负载，在这些场景中，降低开关活动可能值得接受受控数值误差。
Mohamed Niazy, Haytham Azmi, M. M. Mahmoud
Scientific Reports · 2026-06-21
The paper proposes a RISC-V-based cryptographic co-processor architecture for IoT devices, supporting AES-128 and SHA-256 without adding custom instructions to the base ISA. It uses memory-mapped I/O and DMA to move data between memory and cipher units without stalling the processor pipeline, and the design is implemented on a Xilinx ZCU-102 FPGA using Vivado 2022.2. The main significance is a modular security path for constrained devices that need hardware acceleration without fragmenting software compatibility.
这篇论文提出一种面向IoT设备的RISC-V密码协处理器架构，在不向基础ISA添加自定义指令的情况下支持AES-128和SHA-256。设计使用MMIO和DMA在存储器与密码单元之间搬运数据，避免阻塞处理器流水线，并在Xilinx ZCU-102 FPGA上用Vivado 2022.2实现。其主要意义在于为资源受限设备提供模块化硬件安全加速，同时不破坏软件兼容性。
Arnur Kabdylkak, Miras Zhumabek
TSARKA Science · 2026-06-16
The article analyzes DPDK components such as EAL, poll-mode drivers, rte_mbuf, rte_mempool, rte_ring, and several packet-processing models for 100 Gbps-and-above systems. It highlights kernel bypass, zero-copy data paths, cache-optimized processing, and cryptographic protection through rte_security and cryptodev. The FPGA discussion makes it relevant for network accelerators where switching and inline encryption increasingly move closer to hardware.
这篇文章分析DPDK在100Gbps及以上系统中的关键组件，包括EAL、轮询模式驱动、rte_mbuf、rte_mempool、rte_ring以及多种包处理模型。论文强调kernel bypass、zero-copy数据路径、缓存优化处理，以及通过rte_security和cryptodev实现的加密保护。其关于FPGA的讨论使其与网络加速器相关，因为交换和在线加密正越来越靠近硬件实现。
AI Accelerators & Edge Hardware
AI加速器与边缘硬件
Larisa Goffman-Vinopal
Electronics · 2026-06-25
The paper proposes an architecture-level method to prioritize fault-injection candidates for systolic AI accelerators, targeting silent data corruption under limited validation budgets. Its evaluation scores the same 21,000 candidate faults across 30 workload, dataflow, and array configurations, including five GEMM-derived workloads, three array sizes, and two dataflows. The practical value is faster triage of MAC, accumulator, and forwarding-path vulnerabilities before expensive downstream validation.
这篇论文提出一种架构级方法，用于在验证预算有限时对脉动阵列AI加速器的故障注入候选进行优先排序，目标是更有效发现静默数据损坏风险。评估在30种工作负载、数据流和阵列配置下，对同一组21,000个候选故障打分，其中包括5个源自GEMM的工作负载、3种阵列尺寸和2种数据流。其实际价值在于，在昂贵的后续验证之前，更快筛查MAC、累加器和转发路径的脆弱点。
R. Nirmala, Malathi Murugesan, Sasikala Duraisamy, V. Senthilkumar
Interactions · 2026-06-23
The paper reports a mixed-signal CMOS VLSI implementation of a spiking echo-state neural network for energy-efficient temporal signal processing. The candidate feed does not include performance numbers, but the topic is relevant because reservoir-style spiking architectures can reduce digital memory movement for streaming signals. The key question for follow-up is whether measured silicon results show enough robustness and programmability for real edge workloads.
这篇论文报告一种面向高能效时序信号处理的混合信号CMOS VLSI脉冲Echo-State神经网络实现。候选摘要未给出性能数字，但该方向重要，因为reservoir式脉冲架构有机会减少流式信号处理中的数字存储搬运。后续需要关注的是，实测硅片结果是否具备足够鲁棒性和可编程性，以支撑真实边缘工作负载。
Venkata Reddy Adama, G. Koteswar Rao, K. Venugopal Rao
International Journal of Advanced Research in Science, Communication and Technology · 2026-06-16
The paper proposes a low-power FPGA architecture for real-time skin-cancer image processing, combining acquisition, preprocessing, lesion segmentation, feature enhancement, lightweight CNN classification, and hardware acceleration. It targets portable screening systems where software-only deep learning can be limited by compute, memory, and power budgets. The listed abstract is architecture-focused, so measured latency, power, and diagnostic accuracy would determine how deployable the design is.
这篇论文提出一种低功耗FPGA实时图像处理架构，用于皮肤癌检测，流程包括图像采集、预处理、病灶分割、特征增强、轻量级CNN分类和硬件加速。它面向便携筛查系统，因为纯软件深度学习往往受算力、存储和功耗预算限制。候选摘要偏架构描述，因此实测延迟、功耗和诊断准确率将决定该设计的可部署性。