Devices & Process
器件与工艺
X. Wu, Y. Liang, D. Liu, M. Lian, et al.
Advanced Functional Materials · 2026-06-16
This paper reports a reconfigurable artificial vision neuron using Ta2O5/PDVT-10-CsPbBr3 quantum dots to combine retina-like and cortex-like spiking in one optoelectronic device. Bias-free optical leaky-integrate-and-fire behavior lets the device stay quiet on static scenes and emit sparse events when intensity changes. The result targets lower bandwidth and energy for edge vision, where moving full image frames to processors is the bottleneck.
这篇论文提出基于Ta2O5/PDVT-10-CsPbBr3量子点的可重构人工视觉神经元，在一个光电子器件中结合类视网膜和类皮层脉冲行为。其无偏置optical LIF响应可在静态场景下保持低活动度，并在光强变化时生成稀疏事件。结果指向低带宽、低能耗的边缘视觉，因为把完整图像帧搬到处理器才是主要瓶颈。
T. Lin, L. Liu, X. Liu, C. Zhou, W. Wang
Advances in Materials · 2026-06-15
The authors propose PdSe2/a-plane GaN heterostructures for polarization-selective UV photosynapse devices and use pre-selenization to raise PdSe2 anisotropy to a dichroic ratio of 16. The integrated device lifts the anisotropic photocurrent ratio from 1.6 to 10.7 and shows relaxation time up to 282 seconds. It is device-level progress for neuromorphic UV sensing, though manufacturability and long-term stability still need proof beyond the reported structures.
作者提出用于偏振选择性紫外光突触器件的PdSe2/a-plane GaN异质结构，并通过预硒化把PdSe2各向异性提高到16的二色比。集成器件把各向异性光电流比从1.6提升到10.7，并显示最高282秒的弛豫时间。这是神经形态紫外传感的器件级进展，但可制造性和长期稳定性仍需要超出当前结构的验证。
Circuits & Architecture
电路与架构
C.-F. Lai, P.-C. Liu, S.-H. Huang, H.-H. Chen
IEEE Internet of Things Journal · 2026-06-15
This work introduces conditional online Softmax, a one-pass algorithm that fuses reduction and normalization to cut memory traffic while preserving numerical stability. A branch-free RISC-V Vector implementation improves performance by 7% over safe Softmax and 43% over the original online Softmax, while manual RVV vectorization beats GCC auto-vectorization by 2.9x. The result is directly relevant to attention and classifier heads on small edge processors.
这项工作提出conditional online Softmax，用单次遍历融合归约和归一化，在保持数值稳定性的同时减少内存流量。其无分支RISC-V Vector实现比safe Softmax快7%，比原始online Softmax快43%，手写RVV向量化比GCC自动向量化快2.9倍。该结果直接面向小型边缘处理器上的attention和分类头。
J. Mo, A. Daftardar, B. GaneshKumar, K. Guo, et al.
arXiv:2606.16146 · 2026-06-15
The paper compares NTT- and SumCheck-based proving primitives for ZeroCheck under a unified hardware-system framework with the same SRAM and off-chip bandwidth budgets. It finds no universal winner: SumCheck tends to win for high-degree polynomials, while low-degree cases depend strongly on available memory. The value is a system-level map for ZKP accelerator designers who otherwise rely on asymptotic arguments or isolated kernels.
论文在统一硬件系统框架下比较ZeroCheck中的NTT和SumCheck证明原语，并控制相同的片上SRAM与片外带宽预算。结果显示不存在通用赢家：高阶多项式通常更适合SumCheck，低阶场景则高度依赖可用内存。其价值在于为ZKP加速器设计者提供系统级地图，而不是只依赖渐进复杂度或孤立kernel。
B. Wang, Q. Xiao, T. Xu, L. Fan, et al.
Science · 2026-06-11
This Science paper demonstrates an integrated programmable optical signal processor that performs nonlinear, DSP-free real-time equalization before detection. The system equalizes eight WDM channels at 1.6 Tb/s aggregate throughput with less than 60 ps latency and tens of femtojoules per bit. If it can integrate cleanly with transceiver stacks, it points to lower-power optical links for large AI clusters.
这篇Science论文展示了一种集成可编程光信号处理器，可在探测前执行非线性、无DSP的实时均衡。系统同时均衡8个WDM通道，总吞吐达到1.6 Tb/s，延迟低于60 ps，能耗为每bit数十fJ。如果能与收发器栈顺利集成，它将指向大型AI集群中更低功耗的光互连。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
N. P. Jouppi, S. Lakshmanamurthy, C. Young, D. A. Patterson
IEEE Micro · 2026-06-14
Google's IEEE Micro retrospective covers TPU v2 through Ironwood and argues that a stable architecture absorbed major workload shifts such as Transformers. Reported gains over eight years include 10x more HBM capacity and bandwidth per node, 100x higher peak node performance, and 3600x higher supercomputer performance. The paper is useful as a roadmap for accelerator resilience, optical circuit switching, built-in self-test, and hardware replay.
Google在IEEE Micro的回顾文章覆盖TPU v2到Ironwood，并认为稳定架构吸收了Transformer等重大工作负载变化。文中给出的八年提升包括单节点HBM容量和带宽提高10倍、节点峰值性能提高100倍、超级计算机级性能提高3600倍。论文对理解加速器韧性、光路交换、内建自测和硬件重放路线有参考价值。
Z. Wang, C. Huang, C.-H. Lung
arXiv:2606.15045 · 2026-06-13
NEURON-Fabric puts low-bit gradient aggregation inside a CXL memory-controller path while preserving a 32-bit floating-point bypass. Cycle-level experiments report a five-cycle aggregation datapath and at most 1.67% exposed runtime overhead in a full LLC-miss regime, with the compute stage hidden under bandwidth pressure. The idea targets distributed LLM training bottlenecks, though the accuracy checks remain early compared with full-scale model training.
NEURON-Fabric把低比特梯度聚合放入CXL内存控制器路径，同时保留32位浮点旁路。周期级实验显示聚合数据通路为5个cycle，在完全LLC miss场景下最多暴露1.67%的运行时开销，并可在带宽压力下隐藏计算阶段。该思路瞄准分布式LLM训练瓶颈，但相较全规模模型训练，其精度验证仍属早期。
X. Zhao, R. Zhang, H. Jia, K. Li, et al.
ACM Transactions on Architecture and Code Optimization (TACO) · 2026-06-12
PyramidFFT rearchitects FFT execution for AI accelerators with large scratchpad memories, using memory-aware nested networks, matrix-aligned butterfly layouts, and real-FFT compression. The paper reports up to an 8.2x efficiency improvement over a baseline that does not exploit the memory hierarchy. It is a reminder that AI accelerator blocks can be useful for memory-bound HPC kernels only when layout and locality are redesigned with the hardware.
PyramidFFT面向拥有大容量scratchpad memory的AI加速器重新设计FFT执行，结合内存感知nested network、矩阵对齐butterfly布局和real FFT压缩。论文报告相较未利用内存层级的baseline最高获得8.2倍效率提升。它提醒我们，AI加速器模块要服务内存受限HPC kernel，必须围绕硬件重新设计布局与局部性。
AI Systems & Algorithms
AI系统与算法
T. Simon, Y.-C. Chen, J.-J. Chen
ACM Transactions on Embedded Computing Systems · 2026-06-11
This paper optimizes flat vector search with a two-step primitive: a bandwidth-efficient binary sketch prefilters candidates, then SIMD rescoring refines the ranking. On a 1.2 million-vector PC dataset it reports more than 120x speedup over a float32 baseline with NDCG@100 of 0.99; on Raspberry Pi 3 it cuts latency by 39x to 59x and energy by 41x. The result is relevant for edge RAG systems where memory bandwidth dominates query cost.
这篇论文用两步原语优化flat vector search：先用带宽高效的二进制sketch预筛候选，再用SIMD重评分细化排序。在包含120万向量的PC数据集上，相比float32 baseline实现超过120倍加速且NDCG@100为0.99；在Raspberry Pi 3上延迟降低39到59倍，能耗降低41倍。该结果适用于内存带宽主导查询成本的边缘RAG系统。
J. Wang, X. Zhou, X. Sun, Y. Zhang, et al.
arXiv:2606.12950 · 2026-06-11
Maestro is a workload-aware scheduler for LLM multi-agent systems, where one user query can trigger an iterative chain of model calls with heavy-tailed decode costs. It predicts each stage's output length and memory demand, then combines hierarchical weight caching, elastic memory provisioning, and latency-aware cluster routing. The paper is useful because agent serving needs scheduling semantics beyond ordinary single-request queues.
Maestro是面向LLM多智能体系统的工作负载感知调度器，在这类系统中，一个用户查询可能触发一串迭代模型调用，并产生长尾decode成本。它预测每个阶段的输出长度和内存需求，再结合分层权重缓存、弹性内存配置和延迟感知的集群路由。论文的价值在于指出agent serving需要超出普通单请求队列的调度语义。