Circuits, Architecture & Reliability
电路、架构与可靠性
A. K. Kakolyris, F. N. Bostanci, A. Olgun, et al.
arXiv:2606.22632 · 2026-06-21
ColumnKeeper is the first mitigation proposed for ColumnDisturb, a read-disturbance effect that spans columns across three consecutive DRAM subarrays rather than a few neighboring rows. Its deterministic variant tracks odd- and even-column activations with two counters per subarray and triggers targeted refresh, while a probabilistic variant trades fixed guarantees for configurable overhead. The work directly addresses a new reliability and security surface, but the available abstract does not expose full-system overhead numbers.
ColumnKeeper是首个针对ColumnDisturb提出的缓解方案；这种读扰动不是局限于相邻行，而是沿列影响连续3个DRAM子阵列。其确定性版本为每个子阵列用两个计数器跟踪奇数列与偶数列激活，并触发定向刷新；概率版本则以可配置开销换取概率性保障。该工作直接回应了新的可靠性与安全攻击面，但现有摘要未给出完整系统开销数据。
H. Luo, İ. E. Yüksel, A. Olgun, et al.
arXiv:2606.22297 · 2026-06-21
Experiments on 112 commercial DDR4 chips from all three major manufacturers show that a row's prior write pattern changes its read-disturbance threshold. Overwriting with opposite data lowers the minimum aggressor activation count needed for a bit flip, while writing the same data twice raises it; the team also observes effects in 32-row majority operations using processing-in-DRAM. The mechanism remains hypothesis-driven, but the broad COTS sample makes the reliability result difficult to dismiss as a single-vendor artifact.
对3家主要厂商共112颗商用DDR4芯片的实验表明，存储行此前的写入模式会改变其读扰动阈值。用相反数据覆写会降低触发位翻转所需的最小攻击行激活次数，而连续两次写入相同数据会提高阈值；团队还在采用DRAM内处理的32行多数操作中观察到影响。其物理机制仍停留在假设层面，但广泛的商用样本使该结果难以被归因于单一厂商特性。
C. Williams, M. Nabeel, G. Chacon, et al.
arXiv:2606.22198 · 2026-06-20
This perspective organizes 2.5D chiplet threats around interconnect attacks, cache-coherence exploits, and microarchitectural side channels, then places an active silicon interposer at the system's root of trust. The architecture is intended to police chiplets and links sourced from mutually untrusted vendors rather than assuming any one die is authoritative. It is a security survey and design argument, not a measured implementation, so its area, latency, and verification costs remain open.
这篇观点论文将2.5D chiplet威胁归纳为互连攻击、缓存一致性利用和微架构侧信道，并把主动式硅中介层置于系统信任根位置。该架构旨在监管来自彼此不可信供应商的chiplet与链路，而不是默认某颗裸片天然可信。论文属于安全综述与设计论证，并非实测实现，因此面积、时延和验证成本仍待回答。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Z. Wang, H. Wang, Y. Xiao, et al.
arXiv:2606.22968 · 2026-06-22
MOCAP targets long-context, prefill-only LLM inference on wafer-scale chips, where causal KV-cache growth creates both memory and pipeline imbalance across sequence chunks. Its memory-balanced KV reallocation and chunked pipeline redistribute state and work so later chunks do not overwhelm individual stages. The architecture addresses a real wafer-scale bottleneck, but the candidate abstract does not provide enough benchmark detail to judge gains across models or hardware implementations.
MOCAP面向晶圆级芯片上的长上下文、纯预填充LLM推理，解决因因果KV-cache持续增长而产生的跨序列分块存储与流水线失衡。其存储均衡KV重分配和分块流水线重新分布状态与计算，避免后续分块压垮个别阶段。该架构瞄准了真实的晶圆级瓶颈，但候选摘要缺少足够的基准细节，尚难判断其在不同模型与硬件实现上的收益。
D. Tokuda, T. Kubo, I. E. Yuksel, et al.
arXiv:2606.22812 · 2026-06-22
Clutch recodes vector values as temporal sequences of leading ones so a scalar comparison becomes a lookup-like DRAM row access rather than a long bit-serial command sequence. Chunked temporal coding is used to contain the otherwise prohibitive lookup-table footprint while preserving the data-movement advantage of processing-using-DRAM. The method is promising for databases and ML filters, but the available abstract does not establish production-DRAM support or measured silicon results.
Clutch把向量值重编码为前导1的时间序列，使标量比较转化为类似查表的DRAM行访问，而不再需要冗长的位串行命令序列。分块时间编码用于控制原本难以接受的查找表容量，同时保留DRAM内处理减少数据搬移的优势。该方法适合数据库和ML筛选操作，但现有摘要未证明量产DRAM支持，也未给出实测硅结果。
X. Ai, Z. Ling, H. Yuan, et al.
arXiv:2606.22482 · 2026-06-21
NeutronSparse addresses sparse matrix multiplication on Ascend 910B, where the official MindSpore implementation reaches only 36.3% of cuSPARSE performance on an Nvidia A100. It partitions work across heterogeneous NPU compute units according to sparsity and reorganizes tiles for locality, treating coordination rather than raw arithmetic as the primary bottleneck. The comparison spans different accelerators and software stacks, so the headline gap should not be read as a hardware-only result.
NeutronSparse针对Ascend 910B上的稀疏矩阵乘法；官方MindSpore实现的性能仅达到Nvidia A100上cuSPARSE的36.3%。它依据稀疏度在异构NPU计算单元间划分负载，并按局部性重组tile，把协同效率而非原始算力视为首要瓶颈。由于比较跨越不同加速器与软件栈，这一性能差距不能简单解读为纯硬件结论。