Scaling Moves Into Devices, Memory, and Context 扩展转向器件、存储与上下文

This week's work attacks bottlenecks from nanoscale interfaces and 3D integration to ferroelectric compute-in-memory and prompt-cache continuity. The strongest results connect measured device behavior with system-level cost, latency, reliability, or thermal limits. 本周研究从纳米界面和3D集成一路推进到铁电存内计算与提示缓存连续性。最有价值的结果把器件实测行为与系统级成本、时延、可靠性或散热限制连接起来。

Look-back window: 7 days · 9 paper(s) 回溯窗口: 7天 · 9篇

Devices & Process 器件与工艺

How Perimeter Scaling Changes Ferroelectric HZO Capacitors 周长缩放如何改变铁电HZO电容器

L. Trupină, Ș. Neațu, L. Pintilie, et al.

Advanced Electronic Materials · 2026-06-18

Measurements on W/Hf0.5Zr0.5O2/p-Ge capacitors spanning 10 µm to 0.1 µm show that switched charge stays nearly constant as sweep rate changes, while the smallest 0.01 µm² devices fall below the current-detection floor because of parasitic capacitance. Submicron capacitors show an apparent rise in remanent polarization as perimeter-to-area ratio increases, pointing to edge-dominated switching. The result matters because geometry and measurement parasitics can masquerade as intrinsic ferroelectric improvement during scaling. 对尺寸从10 µm缩小到0.1 µm的W/Hf0.5Zr0.5O2/p-Ge电容器测量表明，扫描速率变化时翻转电荷基本不变，而最小的0.01 µm²器件因寄生电容影响，其翻转电流低于检测下限。亚微米电容器随着周长面积比提高，呈现出剩余极化增强的表观现象，说明边缘主导的翻转作用正在增大。该结果的重要性在于，缩放过程中几何效应和测量寄生项可能被误判为材料本征铁电性能提升。

CNT CFET Logic Integrates with 3D-Stacked Photodiodes CNT CFET逻辑与3D堆叠光电二极管实现单片集成

Xiao Luo, Haoyu Zhang, Haoyun Liu, et al.

ACS Nano · 2026-06-17

The work monolithically integrates carbon-nanotube complementary FETs in a true vertically stacked CFET layout with 3D-stacked photodiodes, and demonstrates logic gates, a 4-transistor SRAM cell, and a five-stage ring oscillator. Its inverters reach a peak gain of 147 at 1 V and retain a gain of 9.7 with 3.3 pW static power at 0.2 V. This is a measured route toward unified sensing and computing, although the research-scale stack still needs evidence on array yield and process uniformity. 该工作将真正垂直堆叠结构的碳纳米管互补FET与3D堆叠光电二极管进行单片集成，并演示了逻辑门、4晶体管SRAM单元和五级环形振荡器。其反相器在1 V下峰值增益达到147，在0.2 V下以3.3 pW静态功耗仍保持9.7的增益。它为感知与计算一体化提供了实测路径，但研究级堆叠仍需补充阵列良率与工艺均匀性证据。

Van der Waals-Integrable HfOx Dielectric for 2D Transistors 面向二维晶体管的范德华可集成HfOx介质

Nuertai Jiazila, Jiequn Sun, Yunhao Wang, et al.

2D Materials · 2026-06-15

Ultraviolet-ozone conversion of HfS2 produces a van der Waals-integrable HfOx dielectric with an approximately 8.9 MV/cm breakdown field, dielectric constant near 9.6, and leakage around 10^-5 A/cm². MoS2 transistors using the dielectric show an on/off ratio near 10^9, mobility of about 35.3 cm²/V·s, and an 80.2 mV/dec subthreshold swing; floating-gate devices reach a 14 V memory window. The device data are promising for cleaner 2D interfaces, but endurance, wafer-scale uniformity, and integration yield remain open. 通过紫外臭氧将HfS2转化为可进行范德华集成的HfOx介质，其击穿场约为8.9 MV/cm、介电常数约9.6、漏电流约10^-5 A/cm²。采用该介质的MoS2晶体管开关比接近10^9、迁移率约35.3 cm²/V·s、亚阈值摆幅为80.2 mV/dec；浮栅器件的存储窗口达到14 V。这些器件数据有利于构建更洁净的二维材料界面，但耐久性、晶圆级均匀性和集成良率仍待验证。

Circuits, Architecture & Reliability 电路、架构与可靠性

SPINE Profiles Accumulated Bit Flips in Quantized Networks SPINE分析量化神经网络中的累积位翻转

Nathan Guimarães, Ian Kersz, Leonardo R. Gobatto, et al.

arXiv:2606.19526 · 2026-06-17T19:17:08Z

SPINE injects cumulative weight bit flips directly into edge-CPU binaries through GDB, producing per-layer fault profiles without retraining the model or modifying application code. Tests across multiple network topologies, quantization levels, and memory layouts are intended to identify where selective hardening has the most value. The preprint presents a useful profiling method, but it does not report a standardized radiation campaign that would qualify a deployed device. SPINE通过GDB直接向边缘CPU二进制文件中的权重注入累积位翻转，无需重新训练模型或修改应用代码即可生成逐层故障画像。该方法跨多种网络拓扑、量化精度和内存布局进行测试，用于识别最值得选择性加固的位置。这篇预印本提供了实用的分析方法，但并未给出可用于器件认证的标准化辐照测试。

Diamond-Coated Capillary Interposer Targets 3D Hotspots 金刚石涂层毛细结构中介层瞄准3D热点

S. Moore, M. Bauer, S. Moghaddam

IMAPSource Proceedings · 2026-06-17

The proposed 3D-heterogeneous-integration interposer uses laser-machined wick pillars for capillary-fed two-phase cooling and selectively coats them with diamond to improve vertical thermal conduction. Moving evaporation into the packaging layer could remove localized heat without expanding the package footprint. The paper establishes a plausible structure and performance envelope, but package-scale reliability, fluid containment, and manufacturability still need validation. 该3D异构集成中介层采用激光加工的吸液芯柱实现毛细驱动两相冷却，并选择性覆盖金刚石以增强垂直导热。将蒸发界面引入封装层，有望在不扩大封装占地的情况下移除局部热点。论文给出了可行结构和性能边界，但封装级可靠性、流体密封性及可制造性仍需验证。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

FerroNDS Maps Real-Time Forecasting onto Ferroelectric CIM FerroNDS将实时预测映射到铁电存内计算

Keshava Katti, A. Selvakumar, Pratik Chaudhari, et al.

arXiv:2606.16896 · 2026-06-15

FerroNDS maps integrator and oscillator primitives onto multi-bit ferrodiodes, using a 128-neuron system to compute short-time Fourier transforms and forecast signals 500 ms ahead. It reports 1.64 µJ per neuron per inference at 200 Hz and 0.29 µJ at 10 kHz, with a 25–40× area reduction versus SRAM-based digital systems and per-layer latency down to 63.87 µs. The end-to-end mapping is notable, but the preprint's energy and area comparisons need validation across larger models and fabricated arrays. FerroNDS把积分器与振荡器原语映射到多位铁电二极管上，以128神经元系统计算短时傅里叶变换并预测未来500 ms的信号。论文报告在200 Hz下每神经元每次推理能耗为1.64 µJ，在10 kHz下为0.29 µJ；相较基于SRAM的数字系统，面积缩小25–40倍，单层时延最低63.87 µs。端到端映射具有参考价值，但预印本中的能耗与面积对比仍需在更大模型和实际制造阵列上验证。

AI Research & Inference Systems AI研究与推理系统

TokenPilot Preserves Prompt Caches While Compacting Agent Context TokenPilot在压缩智能体上下文时保持提示缓存连续性

Buqiang Xu, Z. Xue, Dian Chen, et al.

arXiv:2606.17016 · 2026-06-15

TokenPilot combines ingestion-aware compaction with lifecycle-aware eviction so long-running agents can remove stale context without repeatedly invalidating reusable prompt prefixes. On PinchBench and Claw-Eval, it reports cost reductions of 56–61% in isolated runs and 61–87% in continuous runs while maintaining competitive task performance. Integration into LightMem2 makes the system reproducible, but broader model providers and production traces are needed to test whether the cache gains generalize. TokenPilot结合摄取感知压缩与生命周期感知淘汰，使长时运行的智能体能够删除过期上下文，同时避免反复破坏可复用的提示前缀。在PinchBench和Claw-Eval上，它报告独立模式成本下降56–61%，连续模式下降61–87%，且任务性能保持竞争力。该系统已集成到LightMem2，便于复现，但仍需通过更多模型服务商和生产轨迹验证缓存收益能否泛化。

Quantum Hardware & Systems 量子硬件与系统

Bath Memory Becomes a Precision Resource in Quantum Transport 环境记忆成为量子输运的精度资源

J. Molina, Sheikh Parvez Mandal, Mahasweta Pandit, et al.

arXiv:2606.17026 · 2026-06-15

The paper derives a dual impedance-matching condition that aligns conductor mode splitting, boundary dissipation, and bath bandwidth in a noninteracting quantum-dot chain. Exact nonequilibrium Green's-function calculations across Lorentzian, Gaussian, and Newns bath spectra show a bandwidth where the current Fano factor is minimized and precision exceeds the Markovian limit. This is a theoretical design rule rather than an experimental demonstration, and its robustness to interactions and device disorder remains open. 论文针对无相互作用量子点链推导出双重阻抗匹配条件，使导体模态分裂、边界耗散与环境带宽相互对齐。对Lorentzian、Gaussian和Newns三类环境谱进行的精确非平衡格林函数计算显示，存在一个可使电流Fano因子最小、精度超越Markov极限的带宽。该结果目前是理论设计准则而非实验演示，其对相互作用和器件无序的鲁棒性仍待研究。

EDA & Design Methods EDA与设计方法

IMPart Integrates Memetic Search into Multilevel Hypergraph Partitioning IMPart将模因搜索集成进多层超图划分

Yugao Zhu, Zhicheng Guo, Shang Liu, et al.

arXiv:2606.18117 · 2026-06-16T16:19:49Z

IMPart moves recombination and mutation directly into the uncoarsening phase of one multilevel hypergraph partitioner instead of invoking separate partitioners for each memetic operation. The design targets large-k partitioning, where conventional high-quality memetic methods often become too slow for practical VLSI use. The candidate abstract does not expose quantitative gains, so the key question is whether solution quality improves enough to justify runtime against current production partitioners. IMPart不再为每次模因操作单独调用划分器，而是把重组与变异直接嵌入单个多层超图划分器的反粗化阶段。该设计面向大k划分问题，因为传统高质量模因方法在此类场景中通常过慢，难以用于实际VLSI流程。候选摘要未给出量化增益，因此关键仍是其解质量提升能否抵消相对现有生产级划分器的运行时间成本。