Circuits & Architectures
电路与体系结构
P. Agnihotri, P. Kalla, S. Blair
arXiv:2606.19674 · 2026-06-18T00:53:05Z
This study compares thermal phase tuning with carrier-based electrical modulation in Mach-Zehnder and microring devices for integrated test and calibration. It evaluates extinction ratio, tuning efficiency, power, bandwidth, and controllability, clarifying when a slower thermal path is preferable to a faster electrical one. The abstract provides design guidance but no headline measurements, so the strength of the comparison depends on the full evaluation methodology.
研究比较了Mach-Zehnder与微环器件中的热相位调谐和载流子电调制，用于片上测试与校准。论文从消光比、调谐效率、功耗、带宽和可控性展开评估，说明何时较慢的热调谐优于更快的电调制。摘要给出了设计取舍，但没有列出关键测量值，因此比较的可信度仍取决于完整评估方法。
S. Zhao, N. Shah, W. Meert, et al.
arXiv:2606.16143 · 2026-06-15T02:59:45Z
AIA is a fabricated 16 nm SoC with a RISC-V host and a 2D mesh of 16 custom RISC-V cores for discrete sampling and approximate inference. Custom instructions and datapaths target non-normalized Knuth-Yao sampling and nonlinear-function interpolation, attacking workloads that map poorly to conventional CPUs and GPUs. The abstract confirms fabrication but does not expose throughput or energy results, which are necessary to judge the specialization cost.
AIA是一款采用16 nm工艺制造的SoC，包含RISC-V主机和由16个定制RISC-V内核组成的二维网格，用于离散采样与近似推理。其定制指令和数据通路面向非归一化Knuth-Yao采样及非线性函数插值，处理传统CPU和GPU映射效率不高的工作负载。摘要确认了芯片制造，但未给出吞吐率或能效结果，因此尚难判断专用化代价。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
G. Koski, S. Lipps, Z. Ma, et al.
arXiv:2606.17500 · 2026-06-16T04:22:06Z
The work maps a quantized, integer-only transformer for CERN jet tagging onto AMD Versal AI Engine tiles, including dense and multi-head-attention layers. Its main contribution is an open-source framework that turns high-level model descriptions into composable AIE blocks and generated Vitis graph code. This is an initial implementation without latency, accuracy, or resource figures in the abstract, so it is more reusable infrastructure than a finished accelerator result.
该工作把用于CERN喷注标记的量化纯整数Transformer映射到AMD Versal AI Engine tile，覆盖全连接层和多头注意力层。主要贡献是一个开源框架，可将高层模型描述转换为可组合AIE模块并生成Vitis图代码。它仍是初步实现，摘要未给出时延、精度或资源占用数据，因此更接近可复用基础设施，而非成熟的加速器结果。
P. K. Sanjaya, C. Giannoula, N. Shreekumar, et al.
arXiv:2606.16809 · 2026-06-15T14:53:13Z
DataGuard adds a hardware control path to systolic-array training accelerators so that only outputs satisfying an owner's differential-privacy budget may leave the device. That removes the assumption that a third-party federated-learning application correctly clips gradients and adds noise. The reported evaluation is simulation-based rather than measured silicon, making area, performance, and integration overhead the key open questions.
DataGuard为脉动阵列训练加速器增加硬件控制路径，只允许符合数据所有者差分隐私预算的输出离开设备。这消除了对第三方联邦学习应用会正确裁剪梯度并添加噪声的信任假设。其评估基于仿真而非实测芯片，因此面积、性能和集成开销仍是关键问题。
G. Alexakis, D. Schoinianakis, G. Dimitrakopoulos
arXiv:2606.16394 · 2026-06-15T08:29:37Z
MPX extends a conventional systolic array to execute both matrix multiplication and direct polynomial multiplication for FHE and post-quantum cryptography. The dual-mode additions cost 20% more area with negligible power overhead during matrix work, while polynomial mode reports more than 1.2 times lower latency than NTT-based mapping on matrix engines. These are experimental design results in a preprint, not a measured production chip.
MPX扩展传统脉动阵列，使其同时执行矩阵乘法以及面向FHE和后量子密码的直接多项式乘法。双模式设计增加20%面积，在矩阵运算时功耗开销可忽略；多项式模式相对在矩阵引擎上映射NTT的方法，时延降低超过1.2倍。这些是预印本中的实验性设计结果，并非量产芯片实测。
AI Research & Inference Systems
AI研究与推理系统
J. Hu, M. Xu, S. Wang, et al.
arXiv:2606.16135 · 2026-06-15
SwiftCache lets models with low KV-cache demand donate idle GPU memory to high-demand models, moving shared prefixes over NVLink instead of reloading them over PCIe from CPU memory or SSD. It also keeps only the active layer's cache locally, creating room for longer multi-turn contexts. The candidate abstract excerpt does not include measured speedups or capacity gains, so workload balance and cross-model interference remain the practical questions.
SwiftCache让KV cache需求较低的模型把空闲GPU显存借给高需求模型，并通过NVLink传输共享前缀，避免经PCIe从CPU内存或SSD重新加载。它还只在本地保留当前活动层的cache，为更长的多轮上下文腾出空间。候选摘要未包含实测加速比或容量增益，因此负载均衡与跨模型干扰仍是实际问题。
F. Chen, H. Chen
arXiv:2606.16332 · 2026-06-15
SMEPilot uses a roofline characterization to choose CPU-only, Arm SME-only, or cooperative execution for each LLM operator shape. It partitions matrix tiles, overlaps matrix and vector stages in attention, and preserves packed layouts to avoid repeated conversion. Tests span Llama-3.2-3B, Qwen3-4B, and Qwen3-30BA3B on phone, PC, and server platforms, but benefits will depend on shared-memory bandwidth and the availability of SME-capable CPUs.
SMEPilot利用roofline分析，按LLM算子形状选择纯CPU、纯Arm SME或协同执行。系统对矩阵tile进行划分，在注意力中重叠矩阵与向量阶段，并保留打包布局以避免重复转换。测试覆盖手机、PC和服务器上的Llama-3.2-3B、Qwen3-4B及Qwen3-30BA3B，但收益取决于共享内存带宽与支持SME的CPU可用性。