Devices & Process
器件与工艺
Yanglin Long, Haozhe Wang, Gangning Lou, et al.
ACS Nano · 2026-06-16
This review connects 2D-semiconductor device work to integrated-circuit requirements, organizing progress around contact resistance, gate-dielectric integration, and dimensional scaling. It also tracks the transition from planar devices to FinFET, GAA, and CFET structures alongside memory and RF demonstrations. The paper is a useful device-to-circuit map, but it is a review rather than new measured silicon and does not resolve the manufacturability gap.
这篇综述把二维半导体器件研究与集成电路需求连接起来，围绕接触电阻、栅介质集成和尺寸缩放梳理进展。文章还追踪了从平面器件到FinFET、全环绕栅极(GAA)和CFET结构的演进，并覆盖存储与RF演示。它提供了一张有用的器件到电路路线图，但属于综述，并未给出新的实测芯片，也没有解决可制造性缺口。
Junguo Xu, Yingying Zhong, Xiongping Bao, et al.
Nanophotonics · 2026-06-12
The work tests high-speed Ge/Si integrated photodetectors under a dose-calibrated broad-spectrum proton beam and evaluates hydrogen loading as a hardening treatment. Untreated devices lose bandwidth and accumulate dark current, while hydrogen-loaded devices retain more bandwidth and limit leakage growth. The measured-device result offers a practical path for space photonics, although long-duration orbital validation is still needed.
该研究在经过剂量标定的宽能谱质子束下测试高速Ge/Si集成光电探测器，并评估氢加载作为辐射加固手段。未经处理的器件出现带宽下降和暗电流累积，而氢加载器件保留了更多带宽并抑制漏电增长。实测器件结果为航天光子学提供了一条可行路径，但仍需长期在轨环境验证。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
Yuehai Chen, Farhad Merchant
arXiv:2606.20414 · 2026-06-18T16:01:08Z
ExSpike keeps every SNN layer in spike form, adds adjacent-position event compression, and includes an attention core for spike-driven self-attention. An AMD Xilinx Virtex-7 FPGA implementation is evaluated on classification and segmentation workloads, showing that irregular event sparsity can be converted into practical execution savings. The evidence is FPGA-based, so ASIC area and energy results remain open.
ExSpike让SNN各层始终保持脉冲形式，引入相邻位置事件压缩，并加入用于脉冲驱动自注意力的attention core。研究在AMD Xilinx Virtex-7 FPGA上针对分类和分割负载进行评估，表明不规则事件稀疏性可以转化为实际执行收益。现有证据基于FPGA，ASIC面积与能耗结果仍待验证。
Keshava Katti, Adithya Selvakumar, Pratik Chaudhari, et al.
arXiv:2606.16896 · 2026-06-15T16:07:05Z
FerroNDS maps continuous-time neural dynamics onto multi-bit ferrodiode compute-in-memory using analog integrator and oscillator primitives. A 128-neuron system forecasts 500 ms ahead at sub-watt power, reporting 0.29–1.64 μJ per neuron per inference and a 25–40× area reduction versus SRAM-based digital systems. The end-to-end ferrodiode integration is notable, but array scaling, process variation, and manufacturability are not yet established.
FerroNDS利用模拟积分器和振荡器原语，把连续时间神经动力系统映射到多比特铁电二极管存内计算硬件。其128神经元系统可在亚瓦功耗下预测未来500 ms，报告每神经元每次推理0.29至1.64 μJ能耗，并较基于SRAM的数字系统缩小25至40倍面积。端到端铁电二极管集成值得关注，但阵列扩展、工艺波动和可制造性尚未得到验证。
Shirui Zhao, Nimish Shah, Wannes Meert, et al.
arXiv:2606.16148 · 2026-06-15T03:06:00Z
AIA combines a RISC-V host with a 2D mesh of 16 customized RISC-V cores for sampling-based approximate inference. The 16nm SoC reaches 1,277 MSample/s at 0.9 V and 20 GSamples/s/W at 0.7 V by using non-normalized Knuth-Yao sampling and direct inter-core register access. Reported gains reach 2× performance and 1.45× energy efficiency over the prior system, though the comparison is specialized to probabilistic-model workloads.
AIA将RISC-V主机与由16个定制RISC-V核心组成的二维网格结合，用于基于采样的近似推理。这颗16nm SoC通过非归一化Knuth-Yao采样和核心间寄存器直接访问，在0.9 V下达到1,277 MSample/s，在0.7 V下达到20 GSamples/s/W。相较前代系统，其报告性能提升最高2倍、能效提升1.45倍，但比较范围集中于概率模型负载。
Norman P. Jouppi, Sridhar Lakshmanamurthy, Cliff Young, et al.
arXiv:2606.15870 · 2026-06-14T15:44:31Z
Google's retrospective from TPU v2 through Ironwood reports 10× growth in HBM capacity and bandwidth per node, 100× higher peak node performance, and 3,600× higher supercomputer performance over eight years. The paper argues that a stable core architecture, optical circuit switching, self-test, and hardware replay absorbed major workload changes without repeated redesign. It is a useful first-party systems history, but not an independent cross-platform benchmark.
Google对TPU v2至Ironwood的回顾显示，八年间单节点HBM容量和带宽提高10倍，节点峰值性能提高100倍，超级计算机性能提高3,600倍。论文认为，稳定的核心架构、光路交换、自测试和硬件重放，使系统能够吸收重大工作负载变化而无需反复重构。它是一份有价值的第一方系统史料，但并非独立的跨平台基准测试。
AI Research & Systems
AI研究与系统
Jaehoon Kang
arXiv:2606.16106 · 2026-06-15T01:43:55Z
Measurements on Jetson Orin NX show that CPU/GPU-only latency models miss the memory-clock state that determines whether edge inference meets a deadline. Under tight deadlines, an EMC-blind model misses 25–28% of cycles, while an EMC-aware governor cuts misses to at most 1.3% under a 2% QoS budget; median latency shifts by as much as about 45% across two Orin SKUs. The result spans CNN, ViT, and LLM decode workloads, making memory-clock observability a deployment requirement rather than a tuning detail.
Jetson Orin NX上的测量表明，只考虑CPU与GPU频率的延迟模型遗漏了决定边缘推理能否按时完成的存储时钟状态。在严格截止时间下，不感知EMC的模型有25%至28%的周期违约，而EMC感知调度器可在2%的QoS违约预算下把违约率降至最高1.3%；在两款Orin SKU上，中位延迟变化最高约45%。结果覆盖CNN、ViT和LLM解码负载，说明存储时钟可观测性是部署要求，而非简单调优项。
Shun Usami, Venkatram Vishwanath, E. Wes Bethel
arXiv:2606.17104 · 2026-06-14T12:23:29Z
A phase-aware Llama2-7B evaluation finds GPUs consistently stronger in compute-heavy Prefill, while GroqRack delivers lower time per output token in Decode when batching is unavailable. GPUs regain the Decode-throughput advantage as batch size increases, showing that a single tokens-per-second number can invert platform conclusions. The scope is limited to one model and current batching support, so the results should guide methodology more than establish a permanent hardware ranking.
一项面向Llama2-7B的分阶段评估发现，GPU在计算密集的Prefill阶段持续占优，而在不支持批处理时，GroqRack在Decode阶段实现更低的单输出token时间。随着batch size增加，GPU重新取得Decode吞吐优势，说明单一tokens-per-second指标可能会反转平台结论。研究仅覆盖一个模型和当前批处理能力，因此更适合作为评测方法指导，而非固定的硬件排名。