Devices & Process
器件与工艺
D. Zhang, X. Zhang, Z. Liang, J. Wu, et al.
Advanced Functional Materials · 2026-06-16
The paper uses a ferroelectric dielectric as an active electrostatic regulator in organic p-n heterojunction optoelectronic synaptic transistors. The switchable polarization field improves exciton dissociation, charge transfer, and recombination suppression, enabling lower-voltage operation for neuromorphic sensing and dynamic machine vision. It is relevant because device-level gain and voltage control are still key barriers for practical in-sensor computing.
该论文在有机p-n异质结光电突触晶体管中使用铁电介质作为主动静电调节器。可切换极化场改善了激子解离、界面电荷转移和复合抑制，从而支持面向神经形态传感和动态机器视觉的低电压工作。其意义在于，器件层面的增益和电压控制仍是实用化传感内计算的关键障碍。
J.-G. Park, Y. Lee, S. Kim, K. Min, et al.
Advanced Functional Materials · 2026-06-16
The authors propose a laminated HZO/HfO2/HZO ferroelectric diode for synaptic devices and reservoir computing. The stack suppresses leakage along vertical grain boundaries, expands the memory window, and produces more gradual polarization switching for improved weight-update linearity. That links materials engineering directly to system-level classification behavior, rather than treating the device as an isolated memory element.
作者提出一种用于突触器件和reservoir computing的HZO/HfO2/HZO三层层压铁电二极管。该堆栈抑制沿垂直晶界的漏电，扩大存储窗口，并通过更渐进的极化切换改善权重更新线性度。这把材料工程直接连接到系统级分类表现，而不是只把器件视为孤立存储单元。
Circuits & RF Systems
电路与射频系统
S. Hauptmeier, K. Braasch, T. Ziegler-Bellenberg, D. P. Cortes N., et al.
arXiv:2606.19536 · 2026-06-17T19:28:43Z
This work reports a measured multistatic J-band radar transmitter and receiver chipset in SiGe BiCMOS with an integrated x16 frequency multiplier chain. The transmitter reaches 11.2 dBm output power and 41 dBm EIRP at 292 GHz with a PTFE lens, while the receiver reports 43.3 dB conversion gain. The result is a concrete circuit contribution for scalable high-frequency radar rather than only a system simulation.
该工作报告了采用SiGe BiCMOS实现并完成测试的多基地J-band雷达发射机和接收机芯片组，片上集成16倍频链。发射机在292GHz下输出功率达到11.2dBm，配合PTFE透镜时EIRP为41dBm；接收机转换增益为43.3dB。这是面向可扩展高频雷达的具体电路成果，而不只是系统仿真。
H. Zhou, H. Chang, D. Widen, C. Fager
arXiv:2606.18395 · 2026-06-16T18:38:15Z
The paper combines CNNs, genetic algorithms, and dual-state impedance synthesis to design pixelated three-port Doherty combiners. Two fabricated GaN HEMT PA prototypes exceed 44.2 dBm saturated output power, reach over 71.2% peak drain efficiency, and maintain up to 64% efficiency at 6 dB back-off. The measured prototypes make this a useful example of AI-assisted RF layout moving beyond purely simulated inverse design.
该论文结合CNN、遗传算法和双状态阻抗综合，设计像素化三端口Doherty合路器。两个已制造的GaN HEMT功放原型饱和输出功率超过44.2dBm，峰值漏极效率超过71.2%，并在6dB回退下达到最高64%效率。实测原型使其成为AI辅助RF版图从纯仿真逆向设计走向硬件验证的有价值案例。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
D. Tokuda, I. E. Yuksel, T. Kubo, A. Olgun, et al.
arXiv:2606.19119 · 2026-06-17T14:32:57Z
PuDGhost identifies an interference mechanism that can corrupt computation results in processing-using-DRAM operations on real DDR4 chips. The study characterizes 96 chips from 12 modules and shows that non-activated rows and concurrently computing columns can affect results under simultaneous multiple-row activation. The paper is important because it turns compute-in-DRAM reliability from an assumed circuit detail into a measured systems risk.
PuDGhost揭示了真实DDR4芯片上Processing-using-DRAM操作可能出现计算结果损坏的干扰机制。研究表征了12个模组中的96颗芯片，显示在同时多行激活下，未激活行以及并发计算的其他列都可能影响结果。该论文重要之处在于，它把DRAM内计算可靠性从默认的电路细节变成了已测量的系统风险。
K. Alexandridis, G. Dimitrakopoulos
arXiv:2606.17781 · 2026-06-16T10:58:02Z
MIVE proposes a programmable integer vector engine that shares one datapath across Softmax, LayerNorm, and RMSNorm. The target is a real LLM inference bottleneck: nonlinear vector operations that are often handled with separate hardware blocks even when matrix multiply dominates total FLOPs. Physical ASIC implementation results indicate better area and hardware efficiency than many standalone accelerators.
MIVE提出一种可编程整数向量引擎，用同一数据通路支持Softmax、LayerNorm和RMSNorm。它瞄准的是LLM推理中的真实瓶颈：虽然矩阵乘法占据总FLOPs主导，非线性向量操作却常由分散专用硬件处理。物理ASIC实现结果显示，其面积和硬件效率优于许多独立加速器方案。
EDA & Design Automation
EDA与设计自动化
C. Wang, Z. Zhuang, S. Jiang, S. Liang, et al.
arXiv:2606.17850 · 2026-06-16T12:20:37Z
CUTh-Solver is a GPU-accelerated sparse matrix solver tailored to high-resolution steady-state and transient thermal simulation for 3D ICs. It exploits regular sparsity in the thermal problem through condensed DIA storage, diagonal-wise SpMV, and preconditioning choices tuned for GPU execution. This is directly relevant to advanced packaging because coarse thermal grids can miss localized hotspots in stacked systems.
CUTh-Solver是面向3D IC高分辨率稳态和瞬态热仿真的GPU加速稀疏矩阵求解器。它利用热问题中的规则稀疏性，通过压缩DIA存储、按对角线SpMV以及面向GPU执行调优的预条件策略提升效率。该工作与先进封装直接相关，因为粗粒度热网格可能漏掉堆叠系统中的局部热点。
Y. Wang, C. Deng, C.-T. Ho, Y. Zhang, et al.
arXiv:2606.17461 · 2026-06-16T03:22:54Z
AUTOGATE proposes an agentic RTL power-optimization flow for fine-grain clock gating. Its ML component compresses long toggling traces into structured representations, while LLM agents rewrite hierarchical RTL modules with correctness constraints. The contribution is notable because it addresses two practical blockers for LLM EDA: waveform scale and large-codebase hierarchy.
AUTOGATE提出一种面向细粒度时钟门控的agentic RTL功耗优化流程。其机器学习组件把长时间翻转波形压缩为结构化表示，再由LLM agent在正确性约束下重写层次化RTL模块。该贡献值得关注，因为它处理了LLM用于EDA的两个实际障碍：波形规模和大型代码库层次结构。
Q. Li, R. Chen, Q. Cheng, C. Wang, et al.
arXiv:2606.17253 · 2026-06-15T19:54:57Z
PDAGENT-BENCH introduces a benchmark for evaluating LLM and vision-language agents across VLSI physical design workflows. It includes 353 curated problems spanning conceptual knowledge, report comprehension, root-cause analysis, script generation, and full-flow implementation. The benchmark is useful because physical design agents need to coordinate EDA tools under strict constraints, not merely answer front-end RTL questions.
PDAGENT-BENCH提出一个用于评估LLM和视觉语言agent在VLSI物理设计流程中能力的基准。它包含353个精选问题，覆盖概念知识、报告理解、根因分析、脚本生成和全流程实现。该基准有价值，因为物理设计agent需要在严格约束下协调EDA工具，而不仅是回答前端RTL问题。