Hardware-Aware AI Moves Into the Loop 硬件感知AI进入闭环

This week's research selection emphasizes measured deployment constraints: resistive memory, FPGA SNN flows, MCU hardware-in-the-loop search, embedded control accelerators, and physical neural-network co-design. The strongest papers treat hardware behavior as part of the model design problem rather than a post-training afterthought. 本期研究更关注可测量的部署约束：阻变存储、FPGA上的SNN流程、MCU硬件在环搜索、嵌入式控制加速器以及物理神经网络协同设计。最有价值的论文把硬件行为纳入模型设计本身，而不是训练后的附加步骤。

Look-back window: 7 days · 10 paper(s) 回溯窗口: 7天 · 10篇

Devices & Process 器件与工艺

Efficient and accurate neural-field reconstruction using resistive memory 利用阻变存储实现高效准确的神经场重建

Y. Yu, X. Zhang, S. Zhang, W. Zhang, X. Wu, et al.

Nature · 2026-06-10

This Nature paper reports neural-field reconstruction using resistive memory, pointing to an analog-memory path for compute-heavy continuous representations. The materiality is that neural fields are bandwidth- and multiply-accumulate-intensive, so moving parts of the computation into memory can reduce data movement. The key caveat is that device variation, programming precision, and array-level scaling decide whether the result becomes a practical accelerator rather than a lab demonstration. 这篇Nature论文报道了利用阻变存储进行神经场重建，展示了面向连续表示计算的模拟存储路径。其重要性在于，神经场计算通常高度依赖带宽和乘加运算，把部分计算移入存储阵列有望减少数据搬运。关键限制仍在器件差异、编程精度和阵列级扩展能力，这些因素决定其能否从实验演示走向实用加速器。

Emerging integrated photonic neural-network technologies for AI 面向AI的新兴集成光子神经网络技术

C. Han, Q. Yang, J. Qin, M. Wang, Z. Yi, et al.

National Science Review · 2026-06-13

This review surveys integrated photonic neural networks from devices through computing cores, integration, and packaging. It is useful because photonic AI hardware is moving from device papers toward system questions such as density, calibration, electro-optic conversion, and packaging. The paper's cross-layer framing helps separate where optics can reduce latency and energy from where electronic control and memory still dominate the cost. 这篇综述从器件、计算核心、集成方式到封装层面梳理了集成光子神经网络。其价值在于，光子AI硬件正在从单一器件论文走向系统问题，包括密度、校准、电光转换和封装。论文的跨层视角有助于区分光学部分能降低延迟和能耗的环节，以及电子控制和存储仍主导成本的环节。

Circuits & Architecture 电路与架构

Real-time offset-free neural-network MPC on embedded systems 嵌入式系统上的实时无偏差神经网络MPC

W.-T. Li, S.-X. Wen, X.-F. Wang, W. Meng, X.-M. Sun

IEEE Transactions on Neural Networks and Learning Systems · 2026-06-11

The paper implements a neural-network model predictive-control framework for aeroengine control and accelerates it on a Zynq DPU. It tackles a practical embedded-control problem: quantized NN predictors can introduce steady-state offsets, so the authors add adaptive error compensation and low-rank linearization. Hardware-in-the-loop experiments make the result more relevant than a pure simulation study. 这篇论文实现了用于航空发动机控制的神经网络模型预测控制框架，并在Zynq DPU上加速。它处理的是实际嵌入式控制问题：量化后的神经网络预测器可能带来稳态偏差，因此作者加入自适应误差补偿和低秩线性化。硬件在环实验让结果比纯仿真研究更具参考价值。

A modular FPGA-based display architecture for low-power real-time avionics 面向低功耗实时航电的模块化FPGA显示架构

C. Albayrak, S. Kurt, M. Kazanbaş

Electronics · 2026-06-09

The authors present an FPGA-assisted smart multi-function display architecture that splits deterministic video processing, application management, LCD, and avionics I/O into separate modules. The design targets timing predictability and subsystem maintainability rather than raw accelerator throughput. It is a useful reminder that FPGA value in embedded systems often comes from deterministic integration and power-aware partitioning. 作者提出了一种FPGA辅助的智能多功能显示架构，将确定性视频处理、应用管理、LCD和航电I/O拆分为独立模块。该设计关注时序可预测性和子系统可维护性，而不是单纯追求加速器吞吐。它提醒我们，FPGA在嵌入式系统中的价值往往来自确定性集成和功耗感知的任务划分。

Breaking TinyML: domain-specific security analysis for quantized neural networks 破解TinyML：量化神经网络需要领域专用安全分析

J. Huckelberry, A. M. Garavagno, Y. Zhang, P. Beerel, J. Mickens, V. Reddi

IEEE Micro · 2026-06-12

This IEEE Micro paper argues that TinyML security needs attacks and defenses tailored to quantized neural-network hardware. The authors show that a two-step attack pipeline can beat prior approaches in the QNN setting, challenging the assumption that quantization robustness transfers cleanly from full-precision models. For edge accelerators, the implication is that model compression, hardware arithmetic, and adversarial behavior must be evaluated together. 这篇IEEE Micro论文指出，TinyML安全需要针对量化神经网络硬件设计专门的攻击与防御方法。作者展示了一个两阶段攻击流程在QNN场景中可超过既有方法，挑战了量化鲁棒性可从全精度模型直接迁移的假设。对边缘加速器而言，这意味着模型压缩、硬件算术和对抗行为必须联合评估。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

CREST: deployment-realistic hardware-in-the-loop NAS for embedded sensing CREST：面向嵌入式感知的部署真实硬件在环NAS

J. Q. Zales, P. Sharma, M. Srivastava

arXiv:2606.15004 · 2026-06-12

CREST searches neural architectures using hardware-in-the-loop measurements on low-power MCU sensing systems rather than relying on proxies such as FLOPs. On inertial odometry, the paper reports a 41.7% median per-inference energy reduction versus FLOPs-based search. The result is important because real deployment schedules, backends, quantization, and target boards can reorder the Pareto frontier. CREST使用低功耗MCU感知系统上的硬件在环测量来搜索神经网络架构，而不是依赖FLOPs等代理指标。在惯性里程计任务上，论文称相对基于FLOPs的搜索，每次推理能耗中位数降低41.7%。该结果重要之处在于，真实部署节奏、后端、量化方式和目标板卡都会重排Pareto前沿。

SupraSNN exploits synapse-level parallelism in SNN accelerators SupraSNN在SNN加速器中利用突触级并行

S. S. Ghavami, M. H. Nikkhah, M. R. Roshanshah, S. Safari

arXiv:2606.13354 · 2026-06-11

SupraSNN treats synaptic events as parallel micro-operations and proposes a superscalar-inspired SNN accelerator. The architecture separates synapse and neuron computation, using multicast and merge trees to expose parallelism while avoiding duplicated neuron-state hardware. The work is relevant because SNN efficiency often depends less on neuron equations than on mapping sparse events onto real datapaths. SupraSNN将突触事件视为可并行执行的微操作，并提出了一种受超标量处理器启发的SNN加速器。该架构分离突触计算和神经元计算，通过多播树和合并树暴露并行性，同时避免重复配置神经元状态硬件。这项工作有意义，因为SNN效率往往不只取决于神经元方程，更取决于稀疏事件如何映射到真实数据通路。

Spiking neural-network inference on FPGAs with hls4ml 使用hls4ml在FPGA上部署SNN推理

B. Dillon

arXiv:2606.10008 · 2026-06-08

This paper extends hls4ml so spiking neural networks trained in PyTorch can be synthesized into FPGA firmware. The demonstration uses a dense quantized SNN on Heidelberg Spiking Digits and reports about 34 microseconds of inference latency. It is a practical tooling contribution because many real-time scientific systems still deploy on synchronous FPGAs rather than asynchronous neuromorphic chips. 这篇论文扩展了hls4ml，使PyTorch训练的脉冲神经网络可以综合为FPGA固件。作者在Heidelberg Spiking Digits数据集上演示了一个密集量化SNN，报告推理延迟约34微秒。其工具链价值较强，因为许多实时科学系统仍部署在同步FPGA上，而不是异步神经形态芯片上。

EDA & Hardware Co-Design EDA与硬件协同设计

LLM-guided NAS for robust co-design of physical neural networks 用于物理神经网络鲁棒协同设计的LLM引导NAS

T. King, T. Leleu

arXiv:2606.10294 · 2026-06-09

UH-NAS uses language models as evolutionary operators while swapping in different unconventional-hardware backends, energy models, precision limits, and non-ideality simulators. The paper tests optical MZI hardware and reports more diverse, robust architectures than conventional baselines. The important idea is not that an LLM designs hardware alone, but that search can reason across accuracy, energy, and physical non-idealities in one loop. UH-NAS将语言模型作为进化搜索算子，同时接入不同非常规硬件后端、能耗模型、精度限制和非理想性仿真器。论文在光学MZI硬件上测试，并报告其找到的架构比传统基线更多样且更鲁棒。重要思想不是让LLM独立设计硬件，而是让搜索在同一闭环中同时权衡精度、能耗和物理非理想性。

Quantum & Emerging Computing 量子与新型计算

Measurement circuit ansatz: Naimark versus quantum neural-network measurements 测量电路Ansatz：Naimark与量子神经网络测量

S. Yun, T. Kyaw, J. Bae

arXiv:2606.07376 · 2026-06-05

The authors compare Naimark-based measurement circuits, hybrid Naimark-QNN circuits, and fully parameterized QNN measurements for general quantum measurements. The reported result is that QNN circuits can approach near-optimal measurements with fewer training iterations in state-discrimination tasks. For quantum hardware, measurement compilation is a real systems problem because readout strategy affects both fidelity and circuit resource cost. 作者比较了基于Naimark扩展的测量电路、混合Naimark-QNN电路以及全参数化QNN测量，用于实现一般量子测量。论文报告称，在态判别任务中，QNN电路可用更少训练迭代接近最优测量。对量子硬件而言，测量编译是实际系统问题，因为读出策略会同时影响保真度和电路资源成本。