Devices & Process
器件与工艺
W. Chen, D. Tang, C. Luo, et al.
ACS Nano · 2026-06-09
The paper demonstrates an all-2D ferroelectric gate-all-around FET aimed at low-power 3D-integrated logic and edge neuromorphic computing. Reported device metrics include sub-60 mV/dec switching down to 25.3 mV/dec, an on/off ratio of 10^8, and mobility of 310 cm2/V/s. The important result is the combination of steep switching, compact logic, and leaky-integrate-and-fire neuron behavior on one hardware platform, though manufacturing integration remains the key caveat.
论文展示了一种全二维铁电环绕栅FET，面向低功耗3D集成逻辑和边缘神经形态计算。报道的器件指标包括低至25.3 mV/dec的亚60 mV/dec开关、10^8开关比以及310 cm2/V/s迁移率。关键结果是把陡峭开关、紧凑逻辑和LIF神经元行为结合在同一硬件平台上，但制造集成仍是主要挑战。
K. Xu, Z. Guan, M. Pei, et al.
National Science Review · 2026-06-12
This work reports a kappa-phase Ga2O3 in-sensor reservoir-computing system that combines deep-UV sensing, memory, and neuromorphic computation. The device operates across -270 C to 210 C and under ion irradiation with an average flux of 1 x 10^4 rad/s, while reaching up to 95% classification accuracy on astrophysical-event tasks. It is notable because ultra-wide-bandgap semiconductors are usually valued for harsh-environment electronics, and here they are tied directly to compute-in-sensor functionality.
这项工作报道了基于κ相Ga2O3的传感器内储备计算系统，将深紫外传感、存储和神经形态计算结合起来。器件可在-270 C到210 C范围内工作，并承受平均1 x 10^4 rad/s的离子辐照，同时在天体事件分类任务上达到最高95%准确率。其亮点在于，超宽禁带半导体通常用于严苛环境电子，而这里被直接连接到传感器内计算功能。
S.-Y. Zheng, Y.-C. Sun, Y.-C. Kao, et al.
Advanced Electronic Materials · 2026-06-10
The authors use temperature-graded ALD deposition for Hf0.5Zr0.5O2 ferroelectric capacitors to improve polarization and reliability together. They report 2Pr of 39.6 uC/cm2 at +/-3 V, endurance up to 2 x 10^9 cycles, and projected 94.0% polarization retention over 10 years at 85 C. The process angle matters because HZO ferroelectrics need reliability gains before they can move deeper into memory and logic products.
作者采用温度梯度ALD沉积Hf0.5Zr0.5O2铁电电容，同时改善极化和可靠性。论文报道在+/-3 V下2Pr为39.6 uC/cm2，耐久性达到2 x 10^9次循环，并预测在85 C下10年后仍保留94.0%极化。这个工艺路线重要，因为HZO铁电材料要进入更多存储和逻辑产品，可靠性提升是前提。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
X. Hu, C. Liu, Y. Ding, et al.
ACM Transactions on Embedded Computing Systems · 2026-06-10
HyPIM proposes a 3D processing-in-memory architecture that combines SRAM and ReRAM slices for transformer inference. The motivation is that different transformer-block operations stress compute and memory in different ways, so a single memory technology is a poor fit. The paper is useful because it treats LLM inference as a heterogeneous memory-system problem, while still facing the practical challenge that attention latency can dominate end-to-end performance.
HyPIM提出一种结合SRAM和ReRAM切片的3D存算一体架构，用于Transformer推理。其动机是，Transformer block中的不同操作对计算和存储的压力不同，单一存储技术难以适配。论文价值在于把LLM推理视为异构存储系统问题，但仍需面对attention延迟可能主导端到端性能的实际挑战。
A. A. Fereidani, M. R. Roshanshah, S. Safari
arXiv:2606.13560 · 2026-06-11
ReSCom is a reconfigurable spiking-neural-network accelerator that uses stochastic arithmetic for multiplication while keeping fixed-point addition and subtraction exact. The design supports IF, LIF, and synaptic neuron models in one hardware framework and exposes runtime trade-offs between accuracy, latency, and energy. The FPGA result on MNIST reports 92.80% accuracy, making the work a concrete hardware-efficiency study rather than only an algorithm proposal.
ReSCom是一种可重构脉冲神经网络加速器，在乘法中使用随机算术，同时保持定点加减法精确。该设计在同一硬件框架中支持IF、LIF和突触神经元模型，并提供准确率、延迟和能耗之间的运行时权衡。其FPGA MNIST结果报告92.80%准确率，使这项工作更接近具体硬件效率研究，而不只是算法方案。
Z. Yan, J. Mao, K. Tang, et al.
arXiv:2606.13016 · 2026-06-11
Otters++ uses the natural decay of an In2O3 optoelectronic synapse to implement the temporal term in time-to-first-spike coding. The paper then builds a training path for Transformer-style models by linking the SNN computation to an equivalent quantized neural network with distillation. The result is interesting because it converts a device behavior that is often treated as a nuisance into a compute primitive, but scalability depends on device variation and integration.
Otters++利用In2O3光电突触的自然衰减来实现首脉冲时间编码中的时间项。论文进一步通过把SNN计算与等效量化神经网络和蒸馏训练连接，为Transformer类模型建立训练路径。其有趣之处在于把常被视作麻烦的器件行为转化为计算原语，但可扩展性取决于器件变异和集成能力。
EDA & Hardware Security
EDA与硬件安全
Y. Li, Y. Xia, G. Zhong, et al.
ACM Transactions on Design Automation of Electronic Systems · 2026-06-12
CGNet predicts physical-design congestion by jointly processing feature maps and heterogeneous graphs. The paper emphasizes graph compression and cross-stitch fusion to keep inference light enough for time-critical design-loop use. This matters because early congestion visibility can prevent costly routing iterations, but EDA adoption will depend on robustness across process nodes, design styles, and tool flows.
CGNet通过同时处理特征图和异构图来预测物理设计拥塞。论文强调图压缩和cross-stitch融合，以保持推理足够轻量，可用于时间敏感的设计循环。其重要性在于，早期拥塞可见性可以避免昂贵的布线迭代，但EDA采用仍取决于其跨工艺节点、设计风格和工具流程的稳健性。
A. G. Gener, A. Roll'on de Pinedo
arXiv:2606.09213 · 2026-06-08
SNN-MLIR introduces an out-of-tree MLIR dialect and a NIR-to-MLIR-to-C bridge for spiking neural networks. The goal is to turn framework-neutral SNN descriptions into a transformable compiler representation that can target simulation and hardware-oriented deployment. The paper matters because neuromorphic hardware needs compiler plumbing as much as new neuron circuits; without it, trained SNNs remain difficult to move across backends.
SNN-MLIR提出一个外部MLIR方言，以及面向脉冲神经网络的NIR到MLIR再到C的编译桥。目标是把框架中立的SNN描述转化为可变换的编译器表示，同时服务仿真和面向硬件的部署。这篇论文重要，因为神经形态硬件不仅需要新的神经元电路，也需要编译器基础设施；否则训练好的SNN很难跨后端迁移。
S. K. Abharian, S. M. P. Dinakarrao
arXiv:2606.10163 · 2026-06-08
GRAFT studies backdoor attacks against GNN-based hardware-security detectors by embedding graphlet triggers at RTL or gate level while preserving circuit function. That makes the attack more realistic than arbitrary subgraph triggers, because the modified circuit can still behave correctly. The result is a warning for ML-assisted Trojan and IP-theft detection: model accuracy is not enough if the detector can be steered by structure-preserving triggers.
GRAFT研究针对基于GNN的硬件安全检测器的后门攻击，通过在RTL或门级嵌入graphlet触发器，同时保持电路功能不变。与任意子图触发器相比，这让攻击更现实，因为被修改的电路仍可正确运行。其结果提醒ML辅助的木马和IP盗用检测：如果检测器可被保持结构功能的触发器操纵，单纯模型准确率并不足够。