Hardware Models Meet Real-System Constraints 硬件模型直面真实系统约束

This week's strongest papers test abstractions against calibration data, remote-HBM traffic, ADC limits, cache leakage, and long RTL. The common thread is that useful hardware research increasingly depends on modeling the constraints that simplified benchmarks omit. 本周较有价值的论文把抽象模型放到校准数据、远端HBM流量、ADC限制、缓存泄漏和长篇RTL等真实约束下检验。共同趋势是，硬件研究要产生实际价值，越来越需要建模简化基准所忽略的系统条件。

Look-back window: 7 days · 10 paper(s) 回溯窗口: 7天 · 10篇

Circuits, Architecture & Reliability 电路、架构与可靠性

Re-Evaluating Ramulator 2.0's Real-System Accuracy 重新评估Ramulator 2.0的真实系统建模精度

F. N. Bostanci, H. Luo, A. Olgun, et al.

arXiv:2606.14566 · 2026-06-12

The authors argue that earlier negative results for Ramulator 2.0 came from configuration and simulator-usage errors rather than intrinsic model inaccuracy. They identify four practices for evaluating cycle-level DRAM simulators against real systems. Because this is an extended abstract responding to another study, the claims need independent reproduction, but the dispute is directly relevant to memory-system papers built on simulator comparisons. 作者认为，此前针对Ramulator 2.0的负面结果源于配置和模拟器使用错误，而非模型本身不准确。论文总结了评估周期级DRAM模拟器与真实系统一致性的4项实践。由于这是一篇回应既有研究的扩展摘要，其结论仍需独立复现，但这场争议直接影响大量依赖模拟器比较的存储系统论文。

Partitioned Tags Preserve Cache Isolation and Shared-Write Coherence 分区标签兼顾缓存隔离与共享写一致性

K. Ramkrishnan, S. McCamant, A. Zhai, et al.

arXiv:2606.12259 · 2026-06-10

SCP partitions LLC tags while retaining a shared data pool, aiming to combine strict eviction isolation with write-shared coherence. In gem5, the design reduces Prime+Probe, Flush+Reload, and shared-writable-line attacks to random-guessing outcomes with a reported 2.8% LLC SRAM cost. The evidence is simulation-based, so implementation timing and verification on a real cache remain open. SCP对LLC标签进行分区，同时保留共享数据池，以兼顾严格的驱逐隔离和共享写一致性。在gem5中，该设计使Prime+Probe、Flush+Reload及共享可写缓存行攻击的结果降至接近随机猜测，报告的LLC SRAM开销为2.8%。目前证据来自模拟，真实缓存实现中的时序代价和验证仍待完成。

AI Accelerators & Compute-in-Memory AI加速器与存算一体

Positional Encoding Exposes an ADC Bottleneck in Memristor ASR 位置编码暴露忆阻器语音识别中的ADC瓶颈

B. Hilmes, N. Rossenbach, R. Schlüter

arXiv:2606.13379 · 2026-06-11

Large transformed positional-encoding values are identified as a major source of ADC degradation in memristor-based analog speech-recognition inference. Rebalancing weight and ADC precision bits cuts degradation by about 50% at stable estimated energy, while removing encoding-related linear transforms yields about a 30% reduction when the ADC cannot change. The gains are based on modeled analog execution rather than a reported fabricated array. 论文指出，变换后位置编码产生的大幅值是忆阻器模拟语音识别推理中ADC精度下降的主要来源。重新分配权重位宽与ADC精度位可在估算能耗基本不变时把性能劣化降低约50%；若无法修改ADC，去除与编码相关的线性变换也可降低约30%。这些结果基于模拟执行模型，并未报告已流片阵列。

GEMM Locality Search Finds 90x Swings in Remote-HBM Traffic GEMM局部性搜索发现远端HBM流量可相差90倍

E. Chung, H. Kim

arXiv:2606.11716 · 2026-06-10

A tile-level simulator shows that identical LLM GEMM dimensions can generate up to 90x differences in remote-HBM traffic on multi-chiplet GPUs depending on layout, traversal, and placement choices. An agent-guided search finds a 2D block-swizzle traversal that cuts remote traffic by as much as 5.1x versus the best 1D traversal under round-robin placement. The result elevates CTA traversal to a first-order inter-chiplet design variable, though the study remains simulator-based. 一款tile级模拟器显示，在多chiplet GPU上，相同尺寸的LLM GEMM仅因布局、遍历顺序和数据放置不同，远端HBM流量就可能相差90倍。基于智能体的搜索找到一种2D block-swizzle遍历方式，在轮询放置下相较最佳1D遍历最多降低5.1倍远端流量。结果表明CTA遍历顺序是chiplet间通信的一阶设计变量，但研究仍以模拟为主。

Isolation-Aware Scheduling Targets 100 ms Autonomous-Driving Pipelines 隔离感知调度面向100 ms自动驾驶流水线

C. Zhang, Y. Zhang, C. Xue, et al.

arXiv:2606.10303 · 2026-06-09

The paper schedules many co-located driving DNNs on tile-based accelerators while accounting for both hardware isolation and the cost of stop-migrate-restart reallocations. It targets end-to-end latency below 100 ms despite reported execution-time variation of up to 3.3x and task rates from 10 to 240 Hz. The approach addresses a practical shared-accelerator problem, but the candidate record does not report measured automotive silicon. 该论文面向tile式加速器上密集共置的多种自动驾驶DNN进行调度，同时考虑硬件隔离以及停止、迁移、重启所带来的重分配成本。目标是在执行时间最多波动3.3倍、任务频率为10至240 Hz的条件下，把端到端延迟控制在100 ms以内。它针对真实的共享加速器问题，但候选记录未显示在汽车芯片实物上完成测量。

Hardware-Relevant AI Research 面向硬件的AI研究

Eidola Models Transient Multi-GPU Communication in gem5 Eidola在gem5中建模瞬态多GPU通信

R. R. Selagamsetty, M. Poremba, B. M. Beckmann, et al.

arXiv:2606.12638 · 2026-06-10

Eidola extends gem5 with lightweight GPU traffic models driven by annotated timing profiles from real distributed-AI applications. It reproduces fine-grained peer-to-peer writes and synchronization behavior without simulating every GPU detail, enabling larger interconnect studies. Accuracy therefore depends on how representative the captured profiles are when workloads, kernels, or overlap strategies change. Eidola利用真实分布式AI应用的标注时序轨迹，为gem5加入轻量级GPU流量模型。它无需模拟GPU的全部细节，即可复现细粒度点对点写入与同步行为，从而支持更大规模的互连研究。其准确性因此取决于采集轨迹在工作负载、内核或通信计算重叠策略变化后是否仍具代表性。

A Bit-Exact Catalog Standardizes 84 AI Numeric Formats 位精确目录统一描述84种AI数值格式

D. Vasilev

arXiv:2606.09686 · 2026-06-08

The work catalogs 84 numeric formats across 13 families and supplies bit-exact conformance vectors for BF16, FP8, MXFP4, and related microscaling formats. Cross-checks against ml_dtypes 0.5.4 expose interpretation gaps that can otherwise create silent differences when models move between accelerators. It is reference infrastructure rather than a new arithmetic result, but it could make low-precision validation more reproducible. 该工作整理了13个系列共84种数值格式，并为BF16、FP8、MXFP4及相关微缩放格式提供位精确一致性向量。与ml_dtypes 0.5.4的交叉检查揭示了可能导致模型跨加速器迁移时出现静默差异的解释分歧。它不是新的算术方案，而是一套参考基础设施，有助于提升低精度验证的可复现性。

Quantum Computing 量子计算

Apollo Integrates 10,000 Room-Temperature p-Qubits in 16 nm CMOS Apollo以16 nm CMOS集成1万个室温p-qubit

A. Ivanov, S. Rahmeh, E. G. S. Nascimento, et al.

arXiv:2606.12968 · 2026-06-11

Apollo is reported as a 10,000-node p-qubit neuromorphic processor fabricated in 16 nm mixed-signal CMOS, operating at room temperature with about 0.5 W of analog-core power. Integrated quantum entropy drives stochastic state transitions, while a high-degree interconnect targets dense Ising and QUBO embeddings without cryogenic control. The scale and power claims are notable, but the preprint's quantum-advantage framing requires careful independent benchmarking. Apollo被报告为一款采用16 nm混合信号CMOS制造的1万节点p-qubit神经形态处理器，可在室温下运行，模拟核心功耗约0.5 W。集成量子熵源驱动随机状态跃迁，高度互连结构则面向稠密Ising与QUBO映射，无需低温控制。其规模和功耗数据值得关注，但预印本关于量子优势的表述仍需严格的独立基准验证。

Calibration-Aware Routing Raises Simulated IBM Heron Fidelity 校准感知路由提升IBM Heron模拟保真度

Y. V. Tomar, D. Peddireddy, V. Aggarwal

arXiv:2606.12816 · 2026-06-11

A graph reinforcement-learning router uses same-day IBM Heron r2 calibration data to choose SWAP operations, reaching pooled mean simulated fidelity of 0.727 versus 0.440 for SABRE-best20. The improvement comes with more two-qubit gates and is concentrated in 5- and 8-qubit circuits; all tested 10-qubit families favor SABRE-best20 under the fixed action graph. The results are exact simulations rather than executions on the quantum processor. 一种图强化学习路由器利用IBM Heron r2当日校准数据选择SWAP操作，汇总平均模拟保真度达到0.727，而SABRE-best20为0.440。提升伴随更多双量子比特门，且主要集中在5和8量子比特电路；在固定动作图下，所有测试的10量子比特电路族仍由SABRE-best20占优。结果来自精确模拟，并非量子处理器实机执行。

EDA & Design Automation EDA与设计自动化

LongRTL Uses Graph Similarity to Optimize Large RTL Designs LongRTL利用图相似度优化大型RTL设计

Y. Ye, C.-K. Shen, X. Hu, et al.

arXiv:2606.08944 · 2026-06-08

LongRTL divides large RTL designs into AST subtrees, optimizes them with retrieval-guided agents, and reconstructs the design while checking global functional equivalence. Graph similarity supplies reusable structural guidance intended to move LLM-based RTL optimization beyond short toy modules. The abstract does not provide tape-out results or detailed PPA gains, so the main contribution is the workflow architecture rather than demonstrated silicon impact. LongRTL把大型RTL设计拆分为AST子树，利用检索引导的智能体进行优化，再在检查全局功能等价性的同时完成重构。图相似度为结构复用提供指导，目标是让基于LLM的RTL优化走出短小示例模块。摘要未给出流片结果或详细PPA收益，因此当前主要贡献是工作流架构，而非已验证的硅片效果。