AI Accelerators & Compute-in-Memory
AI加速器与存算一体
J. Wu, L. Jiang, S. Sun, et al.
IEEE TCAS-I · 2026-06-01
The design combines a 10T SRAM compute cell, multicycle capacitive weighting, and a reconfigurable SAR ADC that can operate as one 8-bit converter or two 4-bit converters. In 28nm simulation it reaches 15.56 TOPS/W for a 12-bit 8+4 configuration, targeting the efficiency gap between analog and digital CIM. The result is simulation-only, so array nonidealities and measured silicon overhead remain open.
该设计结合10T SRAM计算单元、多周期电容加权，以及可在单个8-bit ADC和两个并行4-bit ADC之间切换的SAR ADC。在28nm仿真中，12-bit的8+4配置达到15.56 TOPS/W，目标是缩小模拟与数字CIM之间的效率差距。结果仅基于仿真，阵列非理想性和实测芯片开销仍待验证。
R. Wang, D. Zhang, S. Yao, et al.
ACM TACO · 2026-05-29
HVPU couples a conventional vector processing unit with compute-capable SRAM through a common frontend interface, dynamic hazard handling, and concurrent dispatch. Multiple PIM blocks and dual control pipelines aim to expose SRAM-array parallelism without forcing software to manage two disconnected engines. The architectural integration is the main contribution; the candidate record does not provide measured-silicon evidence.
HVPU通过统一前端接口、动态冒险处理和并发分派，把传统向量处理单元与具备计算能力的SRAM连接起来。多个PIM模块和双控制流水线用于释放SRAM阵列并行度，同时避免软件管理两个彼此割裂的执行引擎。论文的主要贡献在于架构集成，候选记录未提供实测芯片证据。
Circuits & Architecture
电路与架构
Y. Zhao, Z. Xie, R. Zhan, et al.
IEEE TCAD · 2026-06-01
NTT-LSU integrates a configurable number-theoretic-transform engine directly with a RISC-V load-store unit and adds custom NTT and inverse-NTT instructions. A hybrid-width datapath reduces transfer overhead while retaining support for multiple lattice-cryptography parameter sets. The approach attacks data movement rather than only arithmetic latency, which is important for practical post-quantum processors.
NTT-LSU把可配置的数论变换引擎直接集成到RISC-V访存单元，并增加NTT与逆NTT定制指令。混合位宽数据通路降低了数据传输开销，同时支持多种格密码参数配置。该方案不只优化算术延迟，也直接处理数据搬运问题，这对实用后量子处理器尤为重要。
Y. Tsai, W. Lin, C. Shen, et al.
IEEE TVLSI · 2026-06-01
The detector combines approximate expectation propagation with Chebyshev-accelerated Richardson iteration to preserve near-optimal detection under correlated channels. Its VLSI architecture reports 18.7% lower latency and 17.3% less hardware complexity than a prior design targeting correlated channels. The key result is avoiding channel-specific processing that otherwise raises both area and delay.
该检测器把近似期望传播与Chebyshev加速Richardson迭代结合，在相关信道下维持接近最优的检测性能。其VLSI架构相较此前面向相关信道的设计，延迟降低18.7%，硬件复杂度下降17.3%。核心价值在于避免会同时增加面积和延迟的信道特定处理。
F. Pizarro Diaz, B. Robinson, J. Patarroyo Montenegro
Electronics 15(11) · 2026-06-01
This FPGA soft processor adds a two-lane SIMD integer datapath and split-stage floating-point accumulation for one-dimensional convolution workloads. On an Artix-7 Basys3 board it reports a 6x speedup over MicroBlaze-class soft processors at the same 0.073 W static power, with 44% higher dynamic power. The evidence is measured on FPGA rather than ASIC silicon, but the resource-performance trade-off is directly relevant to wearable inference.
这款FPGA软核处理器为一维卷积加入双通道SIMD整数数据通路和分阶段浮点累加流水线。在Artix-7 Basys3平台上，它相对MicroBlaze级软核实现6倍加速，静态功耗同为0.073 W，动态功耗高44%。结果来自FPGA而非ASIC实测，但其资源与性能权衡对可穿戴推理具有直接参考价值。
R. Mishra, M. Okade, K. Mahapatra
IEEE TCAS-I · 2026-06-01
The Midori-64 implementation uses a 16-bit hybrid serial-parallel datapath and masked S-boxes to balance compactness with resistance to power analysis. The paper reports 55.7% lower area, 62.38% lower power, and 78.2% lower energy for the masked S-box implementation against its comparison baseline. System-level security still depends on the complete masking flow and physical implementation, not the S-box alone.
该Midori-64实现采用16-bit串并混合数据通路和掩码S-box，在紧凑面积与抗功耗分析之间取舍。论文称其掩码S-box相对对比基线，面积降低55.7%、功耗降低62.38%、能耗降低78.2%。系统级安全性仍取决于完整掩码流程和物理实现，而不能只由S-box决定。
L. Laurini, L. Ost, S. Cuenca-Asensi, et al.
Journal of Instrumentation 21(06) · 2026-06-01
MultiRad formalizes a radiation-test method that has been applied from 8-bit microcontrollers to 64-bit processors under 14-MeV and thermal-neutron exposure. The platform has supported 20 journal articles since 2020, indicating reuse across multiple devices rather than a one-off setup. Its value is methodological consistency for reliability comparisons, not a new radiation-hardened circuit.
MultiRad形成了一套辐射测试方法，已用于从8-bit微控制器到64-bit处理器，并覆盖14-MeV中子和热中子辐照。自2020年以来，该平台已支持20篇期刊论文，说明它能够跨多种器件复用，而非一次性测试装置。其价值在于为可靠性比较提供一致方法，而不是提出新的抗辐射电路。