Circuits, Architecture & Reliability
电路、架构与可靠性
J. Yang, Y. Yang, S. Dong, et al.
arXiv:2606.08947 · 2026-06-08T02:50:04Z
NeuDW-CIM implements nonlinear dendrite and K-winner modes in a measured 65-nm compute-in-memory macro using twin 9T ternary bit cells and a reconfigurable nonlinear in-memory ADC. It reports 0.8 pJ per synaptic operation, 97.2% accuracy on N-MNIST, and a 30% reduction in ADC conversion latency through early stopping, providing silicon evidence for more adaptable spiking-network primitives.
NeuDW-CIM采用双9T三值存储单元和可重构非线性存内ADC，在实测65纳米存算一体宏中实现非线性树突与K-winner两种模式。芯片达到每次突触操作0.8 pJ，在N-MNIST上取得97.2%准确率，并通过提前停止将ADC转换延迟降低30%，为更灵活的脉冲神经网络计算原语提供了硅验证。
J. Wang, H. Luo, A. Olgun, et al.
arXiv:2606.07761 · 2026-06-05T18:21:16Z
ScaleDisturb uses asymmetric open times for two aggressor rows to trigger read-disturbance bit flips with fewer activations than prior access patterns. Tests across 196 DDR4 and three HBM2 chips found increased vulnerability in every device examined, underscoring that RowHammer defenses must account for timing patterns beyond simple activation counts.
ScaleDisturb通过让两个攻击行保持非对称的开启时间，以比既有访问模式更少的激活次数触发读扰动位翻转。对196颗DDR4和3颗HBM2芯片的测试显示，所有受测器件的脆弱性均有所增加，说明RowHammer防护不能只统计激活次数，还必须覆盖更复杂的时序模式。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
E. Chung, J. H. Ju, H. Kim
arXiv:2606.11718 · 2026-06-10T06:47:27Z
Chiplet-Contiguous Layout stores chiplet-local GEMM data contiguously so locality-aware placement remains compatible with ordinary page-granularity mapping and requires no OS or hardware changes. Across Qwen 3 30B and Llama 3.1 70B GEMMs, it reduces remote HBM traffic by 24.7x and 19.2x on average versus 4 KB interleaving, making memory layout a practical control point for multi-chiplet GPUs.
Chiplet-Contiguous Layout将各chiplet的本地GEMM数据连续存放，使局部性感知放置能够兼容常规页粒度映射，且无需修改操作系统或硬件。在Qwen 3 30B和Llama 3.1 70B的GEMM负载上，相比4 KB交错映射，远端HBM流量平均分别降低24.7倍和19.2倍，表明内存布局可成为多chiplet GPU的重要优化手段。
Z. M. Enciso, X. Niu, X. Wang, et al.
arXiv:2606.10822 · 2026-06-09T13:04:02Z
This FeFET compute-in-memory engine embeds a write-free Gaussian random-number generator for uncertainty-aware Bayesian inference. The generator consumes 640 aJ per sample and the CIM tile reaches 185 TOPS/W/mm2, addressing the sampling energy and endurance costs that make Bayesian models difficult to deploy on battery-limited platforms.
该FeFET存算一体引擎内置免写入高斯随机数发生器，用于支持具备不确定性感知能力的贝叶斯推理。随机数发生器每个样本仅消耗640 aJ，CIM计算单元达到185 TOPS/W/mm²，针对贝叶斯模型在电池受限平台上的采样能耗与器件耐久性瓶颈提出了硬件方案。
R. Tian, Y. Chen, W. Xu, T. S. Rosing
arXiv:2606.08891 · 2026-06-08T00:33:44Z
PALUTE places lookup-table queries inside monolithic 3D DRAM and generates tables near memory for GEMM and nonlinear operators. Cycle-accurate simulation and RTL synthesis report 1,264 tokens per second at 0.16 W and 12.8x higher energy efficiency than CHIME, though the result remains a modeled design rather than measured silicon.
PALUTE将查表操作放入单片3D DRAM，并在近存储位置为GEMM和非线性算子生成查找表。周期精确仿真与RTL综合显示，其在0.16 W功耗下达到每秒1,264个token，能效较CHIME提升12.8倍；但这些结果仍来自建模与综合，而非实测芯片。
Efficient AI Inference Systems
高效AI推理系统
W. Pang, G. H. Jun, F. Liu, D. Chen
arXiv:2606.11357 · 2026-06-09T18:33:14Z
TileFuse fuses unpacking, dequantization, and GEMM/GEMV into close-to-metal kernels for W4A16 and W8A16 inference on AMD XDNA2 NPUs. Its layouts support GEMM dimensions up to 32K and use the full 4x8 AIE array for GEMV, reducing the software mismatch that often prevents standard quantization formats from running efficiently on client NPUs.
TileFuse面向AMD XDNA2 NPU，将解包、反量化和GEMM/GEMV融合为贴近硬件的W4A16与W8A16内核。其数据布局支持最大32K维GEMM，并让GEMV利用完整的4x8 AIE阵列，从而缓解通用量化格式与客户端NPU软件栈之间的适配低效问题。
H. Guo, N. Guo, W. Wang, et al.
arXiv:2606.08761 · 2026-06-07
APEX4 shows that pure W4A4 performance depends on the ratio between Tensor Core and CUDA Core throughput because group dequantization can shift the bottleneck onto CUDA cores. Its hardware-aware kernels deliver up to 1.66x end-to-end speedup on L40S and 1.78x on RTX 3090 in unmodified vLLM, while the same baseline can slow down on GPUs with a less favorable compute balance.
APEX4指出，纯W4A4推理性能取决于Tensor Core与CUDA Core的吞吐比例，因为分组反量化可能把瓶颈转移到CUDA Core。其硬件感知内核在未经修改的vLLM中，使L40S端到端最高加速1.66倍、RTX 3090最高加速1.78倍；而在计算比例不利的GPU上，同类基线甚至可能变慢。
R. Sanovar, S. Bharadwaj, H. Taneja, M. Qureshi
arXiv:2606.09441 · 2026-06-08T12:50:13Z
SIFT precomputes fine-grained high-attention locations in reusable RAG documents and selectively recomputes them during online prefill. The approach targets a practical failure of KV reuse: transferring cached tensors from disk can be slower than recomputation, while coarse reuse can damage accuracy.
SIFT离线提取可复用RAG文档中的细粒度高注意力位置，并在在线预填充阶段选择性重算。该方法针对KV复用的实际问题：从磁盘传输缓存张量可能比重新计算更慢，而粗粒度复用又可能损害准确率。
EDA & Design Automation
EDA与设计自动化
Y. Wang, Y. Wu, C. Wang, et al.
arXiv:2606.09129 · 2026-06-08T07:26:06Z
OpenOpt replaces inactive SRAM cells with equivalent RC and static-power models, accelerating simulation by up to 61.4x while keeping delay error below 0.22% and power error below 1.68%. On FreePDK45, its joint architecture and device-sizing search reports a 73.6% area reduction and 42.3% lower peak power, though validation on newer process design kits remains an open step.
OpenOpt用等效RC负载和静态功耗模型替代非活动SRAM单元，在读写延迟误差低于0.22%、功耗误差低于1.68%的同时，将仿真速度最高提升61.4倍。在FreePDK45上，联合架构与器件尺寸搜索实现73.6%的面积缩减和42.3%的峰值功耗下降，但仍需在更先进的工艺设计套件上验证。
J. Huang, H. R. Rodriguez, D. Yang, et al.
arXiv:2606.08161 · 2026-06-06T13:20:09Z
AttentionCap uses a physics-aligned Transformer to predict self and coupling capacitance across multiple metal stacks and process nodes. On unseen real designs it reports 0.67% self-capacitance error, 3.99% coupling-capacitance error, and 192x faster inference than CNN-Cap, suggesting a path beyond fixed-node learned extraction models.
AttentionCap采用符合物理结构的Transformer，在多种金属层组合和工艺节点之间预测自电容与耦合电容。在未见过的真实设计上，其自电容误差为0.67%、耦合电容误差为3.99%，推理速度较CNN-Cap快192倍，为突破固定工艺节点的学习式寄生参数提取提供了路径。