AI Accelerators & Compute-in-Memory
AI加速器与存算一体
E. Cohavi, N. B. Agostini, J. Haris, et al.
arXiv:2606.11158 · 2026-06-09T17:40:13Z
The authors extend AXI4MLIR so host buffers are allocated directly in DMA-mapped memory, removing the staging copy from heap memory before accelerator transfers. On a configurable matrix-multiplication accelerator, the change cuts main-memory data movement by as much as 2x and raises accelerator utilization. The work shows that compiler and runtime plumbing can recover performance otherwise lost outside the compute kernel.
作者扩展AXI4MLIR，使主机缓冲区直接分配在DMA映射内存中，从而消除加速器传输前从堆内存进行的中转拷贝。在可配置矩阵乘加速器上，该改动最多将主存数据搬运量降低2倍，并提高了加速器利用率。研究说明，编译器和运行时的数据通路优化可以收回原本损失在计算内核之外的性能。
V. Sharma, X. Fu, J. Haris, J. Cano
arXiv:2606.11117 · 2026-06-09T17:14:44Z
SECDA-DSE combines a structured design-space explorer with an LLM stack using retrieval and iterative feedback to generate FPGA accelerator configurations. The evaluation covers element-wise multiplication, 2D convolution, and matrix transpose through end-to-end SystemC and FPGA execution. The approach could reduce manual search effort, but its value depends on whether generated designs remain reproducible and competitive across larger workloads.
SECDA-DSE将结构化设计空间探索器与采用检索和迭代反馈的LLM模块结合，用于生成FPGA加速器配置。评估覆盖逐元素乘法、二维卷积和矩阵转置，并完成SystemC与FPGA端到端执行。该方法有望减少人工搜索成本，但其价值仍取决于生成设计在更大工作负载上的可复现性和竞争力。
T. Borntrager, S. Fleming, P. Holzinger, et al.
arXiv:2606.11065 · 2026-06-09T16:24:59Z
This work packs arbitrary-width signed and unsigned low-precision operands into wide FPGA multiplier paths by using the DSP block's internal pre-adder. Integrated into AMD FINN, the method reduces LUT use by 21% and improves frames per second per DSP by 36% on UltraNet versus the reference implementation. It directly addresses the mismatch between quantized neural networks and fixed-width FPGA arithmetic resources.
该工作利用DSP模块内部的预加器，将任意位宽的有符号和无符号低精度操作数动态打包到宽乘法数据通路中。该方法集成进AMD FINN后，在UltraNet上相较参考实现将LUT占用降低21%，并把每个DSP对应的FPS提高36%。它直接缓解了量化神经网络与FPGA固定宽度算术资源之间的不匹配。
Efficient AI Training & Inference
高效AI训练与推理
M. Frisella, S. Tiwari, A. Ruan, et al.
arXiv:2606.11169 · 2026-06-09T17:48:41Z
Piper separates high-level distributed-training strategy from runtime implementation through annotations, scheduling directives, and a global training-DAG intermediate representation. It compiles that representation into per-device execution plans, allowing combinations of data, pipeline, expert, and ZeRO-style parallelism without hard-coding each strategy. The abstraction could shorten experimentation cycles, although the supplied candidate abstract does not expose full comparative performance results.
Piper通过模型注解、调度指令和全局训练DAG中间表示，将高层分布式训练策略与运行时实现分离。系统把该表示编译为逐设备执行计划，从而组合数据并行、流水线并行、专家并行和ZeRO类优化，而无需为每种策略硬编码实现。这一抽象可能缩短实验周期，但候选摘要未给出完整的对比性能结果。
W. Liu, H. Shi, Y. Li, et al.
arXiv:2606.11164 · 2026-06-09T17:44:23Z
ReasonAlloc is a training-free method that allocates decoding-time KV-cache capacity hierarchically instead of applying a uniform token-eviction budget. It combines offline layer allocation based on a reported reasoning-demand pattern with online reallocation toward information-rich attention heads. Tests on MATH-500 and AIME 2024 span three reasoning models, but the candidate abstract truncates before the full numerical gains.
ReasonAlloc是一种免训练方法，在解码阶段分层分配KV cache容量，而不是对所有位置采用统一的Token淘汰预算。它结合基于推理需求模式的离线逐层预分配，以及面向高信息量注意力头的在线重分配。测试覆盖MATH-500、AIME 2024和三种推理模型，但候选摘要未完整提供数值提升。
X. Zhou, B. Zhu, Y. Xu, et al.
arXiv:2606.11052 · 2026-06-09T16:17:19Z
The paper finds that chain-of-thought supervised fine-tuning can sharply degrade long-context retrieval in hybrid linear-attention models; HypeNet-9B falls from 67.2% to 9.4% on NIAH-S2 at 256K. The authors trace the failure to short-range-biased updates in query and key projections, then propose QK-Restore, which restores those weights from the pre-fine-tuning checkpoint without retraining. The reported recovery preserves reasoning performance, suggesting post-training evaluations must test memory and reasoning together.
论文发现，思维链监督微调会显著削弱混合线性注意力模型的长上下文检索能力；HypeNet-9B在256K长度的NIAH-S2上从67.2%降至9.4%。作者将问题归因于查询和键投影受到偏向短程模式的更新，并提出QK-Restore，从微调前检查点恢复这些权重而无需重新训练。结果显示该方法可在保留推理能力的同时恢复长程召回，说明后训练评估必须同时检查记忆与推理。
A. Gong, A. M. Carrell, R. Dwivedi, L. Mackey
arXiv:2606.10944 · 2026-06-09T14:48:56Z
Express converts a non-causal attention approximation into a causal one while retaining matching approximation guarantees. Combined with Thinformer, it uses O(s) memory with O(s^2 log^2(n)) compression overhead and an I/O-aware Triton implementation that reportedly outperforms FlashAttention 2. The authors apply it to long-context prefill, KV-cache compression, and memory- or compute-constrained decoding.
Express把非因果注意力近似转换为因果形式，同时保持相匹配的近似保证。与Thinformer结合后，它只需O(s)内存和O(s^2 log^2(n))压缩开销，并通过I/O感知的Triton实现取得了相对FlashAttention 2的加速。作者将其用于长上下文Prefill、KV cache压缩以及内存或算力受限的解码。