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Research digest · Sunday, June 7, 2026 研究摘要 · 2026年6月7日 星期日

Inference Efficiency Moves Into System Design 推理效率进入系统级设计

This week's strongest papers attack long-context costs through shared routing, programmable sparse attention, and non-uniform KV caches. EDA and GPU work extend the same theme by making inter-die routing and extreme-precision arithmetic more explicit optimization targets. 本周最值得关注的论文通过共享路由、可编程稀疏注意力与非均匀KV cache降低长上下文成本。EDA与GPU方向也延续了这一主题,将跨裸片布线和超高精度算术变成更明确的优化目标。

Look-back window: 7 days · 8 paper(s) 回溯窗口: 7天 · 8篇

AI Accelerators & Compute-in-Memory AI加速器与存算一体

GPU Multi-Precision Integer Division at Extreme Bit Widths 面向超高位宽的GPU多精度整数除法

Martin B. Marchioro, Aske N. Raahauge, Marc I. Løvenskjold, et al.

arXiv:2606.06386 · 2026-06-04T16:51:22Z

The paper implements integer-domain Newton division on CUDA for precisions from 2^15 to 2^18 bits, a range not supported by CGBN division. Prefix-sum and multiplication refinements bring measured performance close to the authors' operation-count cost model. The result is specialized rather than a general AI kernel, but it is relevant to GPU workloads in cryptography and symbolic computation that exceed standard big-integer libraries. 该论文在CUDA上实现了全整数域的Newton除法,覆盖2^15至2^18位精度,这一范围不受CGBN除法支持。通过前缀和与多精度乘法优化,实测性能接近作者基于运算次数建立的成本模型。该成果并非通用AI内核,但对超出标准大整数库能力的密码学与符号计算GPU工作负载具有价值。

AI Research & Inference Systems AI研究与推理系统

Pretraining Recurrent Networks Without Unrolling Them 无需循环展开的循环网络预训练

Akarsh Kumar, Phillip Isola

arXiv:2606.06479 · 2026-06-04T17:57:33Z

Supervised Memory Training uses a Transformer encoder to generate one-step memory-transition labels, then trains a nonlinear RNN without backpropagation through time. This creates a time-parallel training path with O(1) gradient length between tokens and outperforms BPTT in the reported language and pixel-sequence experiments. The preprint could make recurrent inference architectures easier to train, but broader model-scale and hardware-efficiency results are still needed. Supervised Memory Training先用Transformer编码器生成单步记忆状态转移标签,再训练非线性RNN,从而避免时间反向传播。该方法形成可按时间并行的训练路径,使任意token间的梯度路径长度为O(1),并在论文报告的语言与像素序列实验中优于BPTT。这项预印本可能降低循环推理架构的训练难度,但仍需更大模型规模与硬件效率数据。

Cross-Layer Sparse Attention Shares One Routing Index 跨层稀疏注意力共享单一路由索引

Yutao Sun, Yanqi Zhang, Li Dong, et al.

arXiv:2606.06467 · 2026-06-04T17:54:04Z

Cross-Layer Sparse Attention computes token-level top-k routing once and reuses the index across decoder layers in a YOCO-style KV-sharing architecture. Sharing both KV state and routing attacks prefill cost, cache capacity, and decode overhead without falling back to coarse block sparsity. The paper reports quality across short- and long-context benchmarks, but the preprint still needs independent end-to-end serving validation. Cross-Layer Sparse Attention在YOCO式KV共享架构中只计算一次token级top-k路由,并在多个解码层复用该索引。同时共享KV状态与路由,可共同降低prefill成本、cache容量和解码开销,又无需退回到较粗粒度的块稀疏。论文在短上下文与长上下文基准上报告了质量结果,但仍需独立的端到端服务验证。

Vortex Turns Sparse-Attention Ideas Into Serving Kernels Vortex将稀疏注意力设计转化为服务内核

Zhuoming Chen, Xinrui Zhong, Qilong Feng, et al.

arXiv:2606.06453 · 2026-06-04T17:48:17Z

Vortex combines a Python-embedded sparse-attention language with a page-centric tensor abstraction and a backend integrated into LLM serving stacks. Algorithms generated and refined through the system reach up to 3.46x the throughput of full attention while preserving accuracy in the reported tests. The useful contribution is programmability plus deployment, although the best results depend on the paper's benchmark and serving environment. Vortex将嵌入Python的稀疏注意力描述语言、以页面为中心的张量抽象,以及集成到LLM服务栈的后端结合起来。通过该系统生成并优化的算法,在论文测试中可达到完整注意力最高3.46倍的吞吐量,同时保持准确率。其关键贡献是把可编程性与部署结合,但最佳结果仍依赖论文所用基准和服务环境。

Agent Memory Gets a Systems-Level Cost Model Agent记忆获得系统级成本模型

Yasmine Omri, Ziyu Gan, Zachary Broveak, et al.

arXiv:2606.06448 · 2026-06-04T17:44:18Z

This study profiles ten agent-memory systems across two benchmark suites and separates construction, retrieval, and generation costs. Its four-axis taxonomy and ten system recommendations expose how designs move work between read and write paths, including scheduling, freshness, and amortization tradeoffs. The characterization is useful for storage-tier and fleet planning, but conclusions may shift as agent workloads and memory implementations mature. 该研究在两套基准上分析了10种Agent记忆系统,并将构建、检索与生成成本分别归因。其四维分类法与10项系统建议揭示了不同设计如何在读写路径之间转移工作,包括调度、新鲜度与成本摊销权衡。这些结果有助于存储分层与集群规划,但随着Agent负载和记忆实现演进,结论仍可能变化。

Tangram Makes Non-Uniform KV Caches Practical Tangram让非均匀KV cache走向实用

Hyungmin Kim, Minsoo Kim, Hongseok Kim, et al.

arXiv:2606.06302 · 2026-06-04T15:41:27Z

Tangram assigns a deterministic memory budget to each attention head, groups heads with similar retention needs into vectorized page tables, and balances work ahead of time. These choices target the fragmentation, scheduling, and kernel-utilization penalties that have limited non-uniform KV-cache compression in multi-turn serving. The architecture is well matched to GPU memory constraints, though the available abstract does not expose enough end-to-end numbers to judge deployment gains. Tangram为每个注意力头分配确定性的内存预算,将保留需求相近的头组织进向量化页表,并提前完成负载均衡。这些设计针对多轮服务中限制非均匀KV cache压缩的内存碎片、调度复杂度与内核利用率损失。其架构与GPU内存约束高度相关,但现有摘要缺少足够的端到端数据,尚难判断实际部署收益。

Quantum Computing 量子计算

Quantum Discovery of Rare Events Without Prior Labels 无需预先标记的量子稀有事件发现

Naixu Guo, Po-Wei Huang, Qisheng Wang, et al.

arXiv:2606.06316 · 2026-06-04T15:54:53Z

The proposed quantum algorithm discovers and samples events below a probability threshold without first identifying which outcomes are rare. It achieves optimal quantum scaling with the threshold, including a quadratic speedup for heavy-tailed systems with nonzero tail mass and a polynomial speedup for stationary stochastic processes. The result is algorithmic rather than an experimental hardware demonstration, so practical advantage depends on state preparation and fault-tolerant resources. 该量子算法无需预先知道哪些结果属于稀有事件,就能发现并采样概率低于阈值的事件。其复杂度随稀有度阈值达到最优量子缩放,对尾部质量非零的重尾系统可获得二次加速,对平稳随机过程则可获得多项式加速。该成果属于算法研究而非实验硬件演示,实际优势仍取决于量子态制备与容错资源。

EDA & Design Methods EDA与设计方法

Routing Models for 2.5D and 3D Multi-Die FPGAs 面向2.5D与3D多裸片FPGA的布线模型

Amirhossein Poolad, Soheil Gholami Shahrouz, Andrew Boutros, et al.

arXiv:2606.06421 · 2026-06-04T17:26:46Z

The authors extend VTR and VPR to model, place, and route a broad range of 2.5D and 3D FPGA inter-die fabrics. Their design-space exploration uses HSPICE models for 7 nm active dies and a 45 nm silicon interposer to quantify how die-crossing technologies affect density and latency. This gives FPGA architects a more realistic open-source path for evaluating stacked designs, but the evidence is simulation-based rather than measured multi-die silicon. 作者扩展了VTR与VPR,使其能够对多种2.5D和3D FPGA跨裸片互连结构进行建模、布局与布线。设计空间探索采用7 nm有源裸片和45 nm硅中介层的HSPICE模型,量化不同跨裸片技术对密度与延迟的影响。这为FPGA架构师评估堆叠设计提供了更真实的开源路径,但证据来自仿真而非多裸片实测硅片。