Memristive SNNs Get Practical; FP4 Variants Multiply; Physical AI Reframes the Bottleneck 忆阻SNN走向实用、FP4变体不断分化、物理AI重新定义推理瓶颈

This week's arXiv push centers on three concrete movements: memristor + spiking-neural-network designs reaching deployable form factors, mixed FP4/INT4 micro-format work right after NVFP4 hit silicon, and a tightening focus on batch-1 inference where the bottleneck story is more nuanced than 'memory-bandwidth-bound.' 本周arXiv主线聚焦三条具体推进：忆阻器+脉冲神经网络（SNN）设计达到可部署形态；NVFP4登陆硅片后混合FP4/INT4微格式工作密集出现；以及对batch-1推理的关注收紧——其瓶颈叙事远比「内存带宽受限」更细致。

Look-back window: 7 days · 8 paper(s) 回溯窗口: 7天 · 8篇

Devices & Materials 器件与材料

Sharp periodic Ge concentration modulations beyond the valley wavevector k₀ in nuclear-spin-free Si quantum wells 在无核自旋Si量子阱中实现超过价电谷波矢k₀的尖锐Ge周期调制 preprintSi spin qubitsMBE

co-authors not extracted

academic team

arXiv:2605.31358 · 2026-05-29

Deterministic valley splitting in Si quantum wells is one of the gating problems for scalable silicon spin-qubit quantum computing — and it requires Ge concentration modulations on the order of the Si valley wavevector k₀ (≈ 9.7 nm⁻¹), which means near-monolayer growth control. This work uses ²⁸Si and ⁷²Ge molecular beam epitaxy to demonstrate Ge-modulated Si quantum wells at periods down to ~2 nm with sharp, well-defined modulations. Practically: the materials growth bottleneck on silicon spin-qubit roadmaps just moved measurably. Si量子阱中确定性的谷劈裂，是可扩展硅自旋量子比特计算的瓶颈问题之一——其要求Ge浓度调制达到Si价电谷波矢k₀（约9.7 nm⁻¹）量级，即需要近单层级的生长控制。本工作以²⁸Si和⁷²Ge分子束外延，演示了周期可低至约2 nm、调制界面清晰的Ge调制Si量子阱。实质意义：硅自旋量子比特路线图上的材料生长瓶颈，发生了可量化的位移。

Memristor-based spiking neural network accelerator for bio-inspired interception tasks 面向仿生拦截任务的忆阻器脉冲神经网络加速器 preprintmemristorSNN

co-authors not extracted

academic team

arXiv:2605.31299 · 2026-05-29

Proposes an analog memristor SNN accelerator that integrates in-memory synaptic computation with analog integrate-and-fire neurons — eliminating the multi-transistor CMOS neuron block that has historically dominated SNN-accelerator area. Demonstrated on a bio-inspired interception task (the kind of low-power, event-driven inference where SNNs theoretically dominate). The interesting move is the device-system pairing: by accepting an SNN-shaped workload rather than trying to run general DNNs, the memristor variability problem becomes manageable rather than fatal. 提出一种模拟忆阻器SNN加速器：将存内突触计算与模拟积分-发放神经元集成，消除历来主导SNN加速器面积的多晶体管CMOS神经元单元。论文在仿生拦截任务（SNN理论上占优的低功耗、事件驱动推理类型）上演示。亮点在器件-系统的搭配：通过接受「SNN形状的负载」，而非试图运行通用DNN，忆阻器器件波动问题从致命变为可控。

In-Memory Computing 存内计算

A reconfigurable computing-in-memory macro with charge-sharing-based weighted accumulator 基于电荷共享加权累加器的可重构存内计算宏 preprintSRAM-CIMADC

co-authors not extracted

academic team

arXiv:2605.30814 · 2026-05-29

An SRAM-CIM macro that addresses the three usual blockers — large ADC overhead, multi-bit input latency, and limited read-bitline voltage swing — via three innovations: an IMADC that occupies just 3% area (a 9× improvement), a bit-serial charge-sharing accumulator that cuts latency, and a configurable 1-7b/2-4b/1-7b in/wt/out format envelope. The contribution isn't a single record-setting metric; it's that all three blockers move simultaneously, which is what's required for an SRAM-CIM macro to actually displace a digital MAC array in practice. 一种SRAM-CIM宏，针对长期以来的三大瓶颈——ADC开销大、多比特输入延迟高、读位线电压摆幅受限——给出三项创新：仅占3%面积的IMADC（较此前方案改进9倍）、基于位串行电荷共享的累加器（降低延迟）、以及1-7b/2-4b/1-7b的输入/权重/输出可配置位宽包络。贡献不在单项极限指标，而在三大瓶颈同时被推进——这正是SRAM-CIM宏在实际场景中真正取代数字MAC阵列所需要的。

HE²: a communication-light heterogeneous architecture for efficient fully homomorphic encryption HE²：面向高效全同态加密的通信轻量化异构架构 preprintFHEheterogeneous

co-authors not extracted

academic team

arXiv:2605.31004 · 2026-05-29

CKKS-style FHE workloads split cleanly into compute-heavy operators (ComOps) and memory-heavy operators (MemOps); existing ASIC-only and NMP-only acceleration efforts hit overhead walls because they optimize for only one. HE² proposes a heterogeneous architecture that places ComOps on a compute-dense ASIC and MemOps on near-memory tiles, with a light-weight on-chip interconnect tuned so the inter-operator data movement doesn't dominate. Relevant to the broader privacy-preserving-AI inference build-out where FHE has been compute-prohibitive for so long that hardware redesign is finally being taken seriously. CKKS型FHE负载可干净地拆分为计算密集型算子（ComOps）与内存密集型算子（MemOps）；现有的纯ASIC或纯NMP加速方案因为只优化其中之一而撞上开销墙。HE²提出异构架构：把ComOps放在计算密集的ASIC上，MemOps放在近存储tile上，并以轻量化片上互连调优——使算子间的数据搬运不会成为新瓶颈。意义在于：在隐私保护AI推理的更大建设浪潮中，FHE长期算力代价过高，硬件重设计终于被严肃对待。

Numerical Formats & Inference 数值格式与推理

MixFP4: enhancing NVFP4 with adaptive FP4/INT4 block representations MixFP4：用FP4/INT4自适应块表示增强NVFP4 preprintNVFP4quantization

co-authors not extracted

academic team

arXiv:2605.31035 · 2026-05-29

NVFP4 — Nvidia's block-scaled FP4 micro-format now landed in Blackwell — uses a single FP4 micro-format (E2M1) per block, which often mismatches the per-block tensor statistics in real LLM weights. MixFP4 extends this by letting each block dynamically choose between E2M1 (range-favored) and E1M2 (precision-favored), reusing the existing NVFP4 scale hierarchy and MMA execution path. The implication is practical: existing NVFP4 silicon can support MixFP4 with software-level changes, which makes the format substantially more deployable than a clean-slate FP4 alternative. NVFP4——英伟达已在Blackwell落地的块缩放FP4微格式——每块只使用单一FP4微格式（E2M1），常与真实LLM权重的块级张量统计不匹配。MixFP4扩展此格式：让每块动态在E2M1（重动态范围）与E1M2（重精度）之间选择，沿用既有的NVFP4标度层级与MMA执行路径。实际意义重要：已有NVFP4硅片可通过软件层改动支持MixFP4——比一种全新清单FP4替代方案更可部署。

Memory-bound but not bandwidth-limited: the physical-AI inference gap in batch-1 LLM decode 受存储约束但并非带宽受限：物理AI在batch-1 LLM解码中的推理鸿沟 preprintedge AILLM decode

co-authors not extracted

academic team

arXiv:2605.30571 · 2026-05-28

Robotics, autonomous-vehicle stacks, and embodied agents typically run single-stream batch-1 LLM decode — a different beast from cloud serving's batched workloads. The standard framing 'batch-1 is memory-bandwidth bound' is true but incomplete: this paper measures three 7-8B-class models on edge accelerators and shows non-bandwidth contributions (KV-cache access patterns, kernel launch overhead, control-flow latency) dominate at the millisecond scale that physical-AI applications actually need. Important re-framing for whether to optimize the silicon for HBM bandwidth or for low-latency dispatch. 机器人、自动驾驶栈与具身代理通常运行单流batch-1 LLM解码——与云端服务的批处理负载本质不同。常见框架「batch-1 受存储带宽约束」是对的但不完整：本文在边缘加速器上测量三款7-8B级模型，证明非带宽因素（KV缓存访问模式、kernel启动开销、控制流延迟）在物理AI应用真正需要的毫秒级时间尺度上占主导。对「硅片应优化HBM带宽还是低延迟分发」这一问题的关键重定义。

Performance & Photonics 性能与光子学

From roofline to ruggedness: decomposing and smoothing the GEMM performance landscape 从Roofline到粗糙度：分解并平滑GEMM性能曲面 preprintGEMMperformance modeling

co-authors not extracted

academic team

arXiv:2605.29752 · 2026-05-28

Demonstrates empirically that adjacent GEMM problems differing by a single 128-element step in N can show 30% different throughput on the same GPU — a 'performance ruggedness' that the roofline model and peak-FLOPs intuition both miss. Proposes treating the full multidimensional performance surface as the analytical object, decomposing its texture rather than summarizing it with a scalar bound. The methodology matters because non-peak workloads dominate real serving, and tuning kernels against a ruggedness model is qualitatively different from tuning against a scalar bound. 实证表明：相邻GEMM问题——仅在N维度上相差128个元素的步长——在同一GPU上可表现出30%的吞吐量差异，这种「性能粗糙度」既被Roofline模型也被峰值FLOPs直觉所忽略。论文提出把完整的多维性能曲面作为分析对象——分解其纹理，而非以标量上界总结。方法论意义在于：真实服务由非峰值负载主导，针对粗糙度模型调优kernel，与针对标量上界调优在性质上不同。

Binary amplitude modulation suppresses noise up-conversion in coherent diffractive optical networks 二元幅度调制可抑制相干衍射光网络中的噪声上变频 preprintphotonic computingD2NN

co-authors not extracted

academic team

arXiv:2605.30820 · 2026-05-29

Establishes a counter-intuitive 'less-is-more' robustness law for coherent optical computing: restricting the modulation manifold from continuous complex-valued amplitudes to binary amplitudes actually suppresses stochastic-noise up-conversion while preserving classification accuracy. Seven-layer binary-amplitude D2NN achieves 90.9% on MNIST and 81.9% on Fashion-MNIST — within 2-4 pp of continuous-modulation D2NN. Practical relevance: binary-amplitude optical components are dramatically cheaper to fabricate than continuous-modulation equivalents, so a robustness law in their favor is a deployment unlock. 为相干光计算建立了反直觉的「以少胜多」鲁棒性定律：将调制流形从连续复振幅限制为二元幅度，反而抑制了随机噪声上变频，同时保持分类精度。七层二元幅度D2NN在MNIST达到90.9%、在Fashion-MNIST达到81.9%——与连续调制D2NN相差仅2-4个百分点。实际意义：二元幅度光学器件的制造成本远低于连续调制对应方案，因此一条对其有利的鲁棒性定律就是部署解锁。