Circuits & Architecture
电路与体系结构
et al. (see paper)
arXiv:2605.18444 · 2026-05-18
Multipliers are the workhorse of AI accelerators — systolic arrays, tensor cores, FPGAs all multiply constantly. NBTI aging shifts threshold voltages on the most-stressed transistors over years; in a multiplier that runs at near-100% utilization for the chip's life, the cumulative drift is real and pushes timing margins out of the window. The paper proposes a designable margin-and-redundancy combination targeted at AI duty cycles specifically. Worth reading because most aging-aware design work has assumed CPU-style bursty utilization, not LLM-serving sustained 90%+.
乘法器是AI加速器的主力单元——脉动阵列、Tensor Core、FPGA本质都在持续做乘法。NBTI老化在受应力最强的晶体管上长期推高阈值电压;在芯片寿命内接近满负载的乘法器中,累积漂移真实且会把时序裕度推出窗口。本文提出针对AI工作负载占空比的可设计裕度与冗余组合。值得一读:既有的老化感知设计大多默认CPU式的突发占用,而非LLM服务式的持续90%+占用。
et al. (see paper)
arXiv:2605.18361 · 2026-05-18
Traditional HA clusters keep a hot standby idle for failover, which both wastes resources and creates single-point-of-failure exposure when the standby drifts out of sync. iHAC integrates compute pooling with availability so the 'standby' capacity does productive work and failover is a routing change, not a resource flip. Concrete architecture proposal with simulation; the interest for AI-serving systems is direct — keeping a hot GPU idle 'just in case' costs more than the workload that displaced it.
传统高可用集群将热备节点闲置以备故障切换,既浪费资源,又因备机长期未同步而构成新的单点风险。iHAC将算力池化与可用性整合,使'备份'容量参与生产负载,故障切换变为路由切换而非资源重置。具体架构方案配仿真;对AI服务系统直接相关——为'以防万一'保留闲置GPU的成本,常常高于被它挤掉的负载本身。
AI Accelerators & Compute-in-Memory
AI加速器与存算一体
et al. (see paper)
arXiv:2605.20047 · 2026-05-19
AES-128 and SHA-256 are fast on a CPU per-op but their *bandwidth* profile is terrible — they sit at the wrong end of a memory bus. The group implements both primitives inside the DRAM via near-memory processing, returning ciphertext/hashes directly without round-tripping plaintext over the CPU bus. The compute saved isn't the headline; the bandwidth saved is. For full-disk encryption and storage-tier hashing — which scale linearly with data volume — this is the right place to put the primitive.
AES-128与SHA-256每次操作在CPU上很快,但其'带宽特征'糟糕——位于内存总线的不利端。作者通过DRAM内近存储处理实现两种原语,直接返回密文/哈希,避免明文在CPU总线上往返。节省的算力不是重点,节省的带宽才是。对于全盘加密与存储层哈希(其规模随数据量线性增长),把原语放在这里才是正确的位置。
et al. (see paper)
arXiv:2605.22015 · 2026-05-21
Video Diffusion Transformers blow up compute because 3D spatio-temporal attention scales with token-count × frames. Most token-reduction methods key on visual-similarity heuristics, which are noisy and over-prune. ORBIS uses the model's own output distribution to decide which tokens carry information for *this* generation and which are safe to drop. Practical: works on existing video-DiT checkpoints without retraining. The conceptual move — let the output decide what the input should be — is the architecturally interesting bit.
视频Diffusion Transformer因三维时空注意力随token数×帧数膨胀而算力暴涨。多数token裁剪方法依赖视觉相似度启发式,噪声大且常误删。ORBIS利用模型自身输出分布判断哪些token对当前生成实际重要、哪些可安全丢弃。实践层面:可直接用于现有video-DiT权重,无需重训。'让输出反过来决定输入应该是什么'的思路才是架构上的关键贡献。
et al. (see paper)
arXiv:2605.17683 · 2026-05-17
Jet-tagging at colliders needs DNN inference inside the trigger pipeline at microsecond latency on tiny inputs — exactly the case where most accelerators waste 80% of die area on instruction fetch and dataflow they don't need. The paper targets AMD's ACAP (Versal) heterogeneous fabric: tensor cores for the multiply, programmable logic for the control, NoC for the data movement. Niche application, but the systematic engineering of 'small model + extreme latency' is the relevant pattern for inference workloads pushing into agentic decode and edge.
对撞机喷注识别需在触发流水线内对小输入做微秒级DNN推理——恰是多数加速器为指令取指与不必要的数据流浪费80%晶元面积的场景。本文以AMD ACAP(Versal)异构架构为目标:Tensor Core执行乘法、可编程逻辑做控制、片上网络处理数据搬移。应用面较窄,但'小模型+极致延迟'的系统化工程,对正朝向Agentic解码与边缘扩展的推理负载,有可移植的范式意义。
AI Research (hardware-relevant)
AI研究(与硬件相关)
et al. (see paper)
arXiv:2605.22428 · 2026-05-21
State-of-the-art AllGather and AlltoAll implementations rely on unicast writes and transmit the same data multiple times across the fabric. The paper observes that the underlying interconnects (NVLink, InfiniBand, modern Ethernet) all support hardware multicast — it's just never been used by the AI-collective implementations. Replacing unicast-by-default with multicast-where-applicable removes the duplicate transmissions at the wire level. Concrete numbers on real clusters; the punchline is that the optimization existed in the hardware for years, and the software left it on the floor.
当前最先进的AllGather/AlltoAll实现依赖单播写入,在网络结构上多次传输相同数据。作者观察到:底层互连(NVLink、InfiniBand、现代以太网)早就支持硬件多播——只是AI集合通信实现从未使用。将默认单播替换为'适用处多播',即可在线缆层面消除重复传输。论文在实际集群上给出具体数字,要点是:该优化在硬件中存在多年,软件却一直未使用。
et al. (see paper)
arXiv:2605.19775 · 2026-05-19
Classic LLM-serving analysis treats prefill as compute-bound and decode as memory-bound. With reasoning-centric architectures generating chains of thought thousands of tokens long, that mental model breaks: the dominant phase is decode, the dominant cost is *capacity* (per-token KV-cache footprint × concurrent requests), and prefill is comparatively cheap. The paper formalizes the regime, gives the right bottleneck taxonomy, and notes that most existing serving optimizations were built for the wrong workload. Required reading for anyone planning capacity around reasoning-model deployment.
经典LLM服务分析将prefill视为算力受限、decode视为内存带宽受限。在生成长达数千token思维链的推理型架构下,该心智模型失效:主导阶段变为decode,主导成本是'容量'(每token的KV缓存占用×并发请求数),prefill反而相对廉价。论文形式化了这一新范式,给出正确的瓶颈分类,并指出多数现有服务优化原本针对的是另一种工作负载。所有围绕推理型模型规划产能的人都应阅读。
et al. (see paper)
arXiv:2605.21603 · 2026-05-20
GPUs underutilize their hardware on most ML workloads — an attention layer leaves the tensor cores idle during softmax, a MoE layer leaves them idle during routing, etc. Overlapping operators with different resource profiles closes that gap, but every existing framework demands invasive, model-specific code changes to do it. DynaFlow exposes a programmable scheduler so the overlap is configured rather than hand-coded. Implementation is in PyTorch; the abstraction is the contribution.
在大多数ML工作负载下,GPU硬件并未充分利用——注意力层的softmax阶段Tensor Core空闲、MoE层的路由阶段Tensor Core空闲。重叠资源占用不同的算子可弥合这一差距,但现有框架需对每个模型做侵入式定制改造。DynaFlow暴露一个可编程调度器,使重叠由配置完成而非手工实现。实现位于PyTorch层;真正的贡献是该抽象本身。