AI Accelerators & Compute-in-Memory
AI加速器与存算一体
et al. (see paper)
arXiv:2605.20717 · 2026-05-21
The macro is real silicon: a 0.85µm² 3T1R ReRAM bitcell driving an AND-based in-memory multiplier that supports both conventional CNN and spiking workloads, with a novel interleaved 10T/28T adder tree to amortize accumulation overhead. The dual-mode CNN/SNN capability is the differentiating claim — most prior CIM macros pick one. Edge-inference targets, not data-center.
该宏为实际流片:0.85µm² 3T1R ReRAM位单元搭配基于AND的存内乘法,同时支持传统CNN与脉冲网络负载,并引入新颖的10T/28T交错加法树以分摊累加开销。'CNN/SNN双模'是其核心差异点——此前的CIM宏多只支持其一。面向边缘推理,而非数据中心。
et al. (see paper)
arXiv:2605.20802 · 2026-05-21
SNN accelerators have advertised event-driven efficiency for years, but most are still layer-by-layer pipelines that wait for the full input window before emitting an output. ELSA implements true elastic inference: confident outputs are emitted as soon as enough spikes accumulate, and downstream layers are gated accordingly. The architectural lesson is that SNN efficiency is fundamentally a scheduling problem, not just a circuit one.
SNN加速器多年来一直宣传事件驱动的能效,但绝大多数仍是逐层流水、等满输入窗口才输出。ELSA实现了真正的弹性推理:在脉冲累积到置信阈值时立即输出,下游层据此被门控。其架构启示是:SNN的能效首先是调度问题,而非单纯的电路问题。
et al. (see paper)
arXiv:2605.20406 · 2026-05-21
Bottom-gate FeFETs using TiO2 channels on HfZrO2 ferroelectric dielectric, reported with high on/off ratios across two gate-stack thicknesses. The novelty is moving the CMOS-back-end-compatible HZO stack into a configuration that supports gradual conductance modulation — the prerequisite for analog weight storage. Single-device characterization only; no array-level retention or endurance data yet.
作者在HfZrO2铁电介质上以TiO2作为沟道,制备底栅FeFET并报告两种栅叠厚度下的高开关比。新意在于将与CMOS后段兼容的HZO体系配置为支持电导渐变调制——这是模拟权重存储的前提。仅为单器件表征,尚无阵列级保持或耐久数据。
AI Research (hardware-relevant)
AI研究(与硬件相关)
et al. (see paper)
arXiv:2605.20315 · 2026-05-21
Most LLM quantization schemes pick a single precision for the whole forward pass; Mix-Quant observes that the prefill phase (compute-bound, error-tolerant due to attention averaging) and the decode phase (memory-bound, error-sensitive) want different precisions. The framework runs prefill at FP4 / INT4 and decode at higher precision, with measured throughput gains on agentic, long-context workloads. The framing — phase as a first-class quantization dimension — is the more durable contribution than any specific schedule.
多数LLM量化方案对整次前向使用统一精度;Mix-Quant注意到prefill阶段(计算密集、对误差宽容)与decode阶段(内存密集、对误差敏感)需要不同精度。框架在prefill使用FP4/INT4,decode使用更高精度,在Agentic长上下文负载上获得实测吞吐量提升。比起具体调度,'阶段作为一等量化维度'这一框架本身更具持久价值。
et al. (see paper)
arXiv:2605.21427 · 2026-05-21
Existing LLM-serving systems treat GPU power as a static datacenter constraint and optimize only batching, scheduling, and parallelism. PALS treats power caps as a first-class control surface, dynamically retuning per-GPU power limits across expert-parallel MoE replicas to match the actual computation cost per token. The reported gains in tokens-per-watt are modest but the architectural shift is the right one: in a memory-bound inference regime, the binding constraint is increasingly thermal, not FLOPS.
现有LLM服务系统将GPU功耗视为数据中心层面的静态约束,只在批处理、调度、并行上做优化。PALS将功耗上限当作一等控制面,在专家并行MoE副本之间动态调整每卡功耗上限,以匹配每token的实际计算开销。论文给出的能效提升不算激进,但架构方向是对的:在内存受限的推理形态下,真正的硬约束越来越是热,而非FLOPS。
et al. (see paper)
arXiv:2605.21100 · 2026-05-21
Modern MoE serving binds each request's attention, MoE communication, and KV cache to a single instance — fine for short prompts, ruinous for long context because attention cost scales with KV-cache size while MoE all-to-all latency scales with batch. NanoCP dynamically splits context parallelism per request, decoupling these two scaling laws. The contribution is small in code but large in implication: MoE serving has to stop pretending requests are uniform.
现代MoE服务系统将每个请求的注意力、MoE通信与KV缓存绑定到单一实例——短提示词没问题,长上下文则灾难性:注意力开销随KV缓存大小增长,MoE的all-to-all延迟随批大小增长,两者的扩展规律相互矛盾。NanoCP按请求动态分配上下文并行度,解耦了这两个维度。代码层改动不大,意义却大:MoE服务必须停止假装请求是同质的。