Wccftech · 17h ago
Wccftech · 17小时前
Cerebras introduced CS-4, a rack-scale system built around three WSE-3 Turbo wafer-scale processors. The company claims that selected generation workloads can run roughly 30 times faster than a conventional GPU rack, but that comparison remains vendor-supplied and workload-dependent. The more durable architectural signal is the emphasis on dense power delivery, low-latency wafer links, and rack-level co-design.
Cerebras发布CS-4机架级系统，核心由三颗WSE-3 Turbo晶圆级处理器组成。公司宣称，在特定生成任务上，其速度约为传统GPU机架的30倍，但这一对比仍来自厂商，且高度依赖具体工作负载。更值得关注的架构信号，是高密度供电、低延迟晶圆互连与机架级协同设计。
The Register · 18h ago
The Register · 18小时前
Google has selected Marvell for custom-silicon programs connected to the TPU ecosystem, including inference, storage, networking, memory-interface, and near-memory functions. Marvell also granted Google a warrant covering nearly 59 million shares, potentially worth about $12.2 billion. The agreement diversifies Google's supply and design options without necessarily displacing Broadcom from the TPU roadmap.
Google选择Marvell参与与TPU生态相关的定制芯片项目，范围包括推理、存储、网络、存储接口和近存计算。Marvell还向Google授予近5900万股的认股权，潜在价值约122亿美元。这项协议扩大了Google的供应与设计选择，但并不意味着Broadcom将被排除出TPU路线图。
Wccftech · 21h ago
Wccftech · 21小时前
AMD says two rack-scale systems planned for 2030 could provide the AI performance of 570 MI300X-era racks while using far less electricity. The claim describes a long-range company target rather than shipping hardware, so it should be read as a roadmap for packaging, networking, memory, and cooling improvements. It nevertheless shows how quickly power efficiency has become a first-order accelerator metric.
AMD表示，计划于2030年推出的两套机架级系统，有望提供相当于570套MI300X时代机架的AI性能，同时显著降低用电量。该说法描述的是长期公司目标，而非已出货硬件，因此更适合作为封装、网络、存储与散热改进的路线图来理解。它仍清楚表明，能效已迅速成为加速器的一级竞争指标。
SemiWiki · 16h ago
SemiWiki · 16小时前
The Hot Chips 2026 program is framing new processors and systems around agentic workloads rather than isolated model execution. That shift matters because long-running agents stress memory capacity, tool orchestration, storage I/O, and network latency differently from batch training. The conference agenda offers an early map of which hardware vendors believe those bottlenecks will become commercial priorities.
Hot Chips 2026议程正围绕智能体工作负载，而非单次模型执行，来组织新处理器与系统架构。长时间运行的智能体对存储容量、工具编排、存储I/O和网络延迟的压力，与批量训练明显不同。会议议程由此提供了一张早期地图，显示硬件厂商认为哪些瓶颈将率先成为商业重点。