AI Demand Meets Supply Discipline — Semi News 2026-06-04

Foundry & Manufacturing 晶圆代工与制造

TSMC warns AI-chip supply will trail demand for years TSMC警告AI芯片供应将多年追不上需求

Bloomberg via Google News · 6h ago Bloomberg via Google News · 6小时前

Bloomberg reports that TSMC's CEO expects chip supply to remain unable to meet AI-fueled demand for years. This is the cleanest signal of the day: the bottleneck is no longer only a near-term CoWoS or HBM allocation issue, but a longer manufacturing-capacity problem. The pricing angle also matters because customers are asking TSMC to expand while the foundry wants a return profile that justifies the capital intensity. Bloomberg报道称，TSMC CEO预计芯片供应在未来多年都难以满足AI驱动的需求。这是今天最清晰的信号：瓶颈不再只是短期CoWoS或HBM配额，而是更长期的制造产能问题。价格信号同样重要，因为客户要求TSMC扩产，而代工厂需要足以支撑高资本开支的回报。

Reuters: TSMC is working to meet demand and would like higher prices Reuters：TSMC努力满足需求，也希望提高价格

Reuters via Google News · 11h ago Reuters via Google News · 11小时前

Reuters says TSMC is working hard to meet chip demand and would like to raise prices. Read together with the supply warning, this frames advanced-node capacity as a scarce industrial resource rather than a commodity service. For AI customers, the practical question is not only whether a node is available, but whether enough wafers, packaging slots and long-term commitments can be secured at acceptable margins. Reuters称TSMC正努力满足芯片需求，并希望提高价格。与供应警告放在一起看，先进节点产能更像稀缺工业资源，而不是普通代工服务。对AI客户而言，实际问题不只是某个节点是否可用，而是能否以可接受的利润结构锁定足够晶圆、封装槽位和长期承诺。

TSMC says CoPoS could scale within years TSMC称CoPoS有望在数年内扩大规模

DigiTimes via Google News · 8h ago DigiTimes via Google News · 8小时前

DigiTimes reports that TSMC's chair said CoPoS could scale within years while downplaying the risk from Intel's Terafab packaging challenge. The strategic point is that TSMC is treating advanced packaging as a roadmap with multiple form factors, not a single CoWoS capacity line. If CoPoS scales, the competitive boundary shifts from process nodes alone to who can turn large-package integration into repeatable manufacturing. DigiTimes报道称，TSMC董事长表示CoPoS可能在数年内扩大规模，同时淡化Intel Terafab封装挑战带来的风险。战略重点在于，TSMC正在把先进封装视作多形态路线图，而不是单一CoWoS产能线。如果CoPoS走向规模化，竞争边界将从单纯制程节点转向谁能把大封装集成做成可复制制造。

Memory & Packaging 存储与封装

SK Group and TSMC broaden HBM and advanced-packaging cooperation SK集团与TSMC扩大HBM和先进封装合作

TradingView via Google News · 6h ago TradingView via Google News · 6小时前

SK Group's chair met TSMC's CEO to broaden cooperation on HBM memory development and advanced packaging. This is not a cosmetic partnership: HBM4 and AI-package roadmaps increasingly require memory vendors and foundries to co-design electrical, thermal and mechanical constraints earlier. The meeting underscores how the AI supply chain is becoming a set of paired commitments, not a spot market for interchangeable parts. SK集团董事长与TSMC CEO会面，扩大在HBM存储开发和先进封装上的合作。这不是表面合作：HBM4和AI封装路线图越来越要求存储厂与代工厂更早共同设计电气、热和机械约束。这次会面说明AI供应链正在变成一组配对承诺，而不是可随时替换零件的现货市场。

DDR4 production restarts as memory shortages ripple through PCs DDR4生产重启，存储短缺波及PC供应链

Tom's Hardware · 2h ago Tom's Hardware · 2小时前

Tom's Hardware reports that DDR4 memory and motherboard production is restarting amid severe memory shortages. That matters because AI-driven capacity allocation is feeding back into older, lower-margin parts that the PC ecosystem still needs. The industry is preparing for a strange transition period: DDR5 is the strategic direction, but DDR4 shortages can still disrupt mainstream systems and repair channels. Tom's Hardware报道称，在严重存储短缺背景下，DDR4内存和主板生产正在重启。这很重要，因为AI驱动的产能分配正在反过来影响PC生态仍然需要的旧制程、低利润部件。行业正进入一个有点反直觉的过渡期：DDR5是战略方向，但DDR4短缺仍会扰动主流系统和维修渠道。

Cooling design becomes a battleground for next-gen AI memory 散热设计成为下一代AI存储竞争战场

The Korea Times via Google News · 7h ago The Korea Times via Google News · 7小时前

The Korea Times says cooling design is emerging as a battleground for next-generation AI memory. This is the HBM4 story beneath the bandwidth headline: higher stacks and tighter packages only ship if heat can be removed predictably. Thermal architecture is becoming part of memory differentiation, especially where memory vendors, foundries and accelerator designers must agree on package-level limits. The Korea Times称，散热设计正在成为下一代AI存储的竞争战场。这是HBM4带宽标题之下的真实问题：更高堆叠和更紧封装只有在热量能被稳定带走时才会出货。热架构正在成为存储差异化的一部分，尤其是在存储厂、代工厂和加速器设计方必须共同接受封装级限制的场景。

Hanmi shows HBM4 and 2.5D AI packaging equipment at Computex Hanmi在Computex展示HBM4与2.5D AI封装设备

Chosunbiz via Google News · 12h ago Chosunbiz via Google News · 12小时前

Hanmi Semiconductor debuted at Computex with HBM4 and 2.5D AI packaging equipment. The timing fits the broader shift in spending from chip designs toward the manufacturing tools that determine whether those designs can be built at volume. Equipment vendors serving bonding, inspection and package assembly are moving closer to the center of the AI hardware cycle. Hanmi Semiconductor在Computex首秀，并展示HBM4和2.5D AI封装设备。这个时间点契合更大的投资转向：资金不只追逐芯片设计，也追逐决定这些设计能否规模制造的工具。服务键合、检测和封装组装的设备供应商，正在靠近AI硬件周期中心。

AI & Accelerators AI与加速器

AMD's Helios MI455X platform surfaces with UALink-over-Ethernet AMD Helios MI455X平台曝光，采用UALink-over-Ethernet

Tom's Hardware · 1h ago Tom's Hardware · 1小时前

AMD's Helios MI455X AI platform has surfaced, with initial systems reportedly using UALink-over-Ethernet interconnects. The design shows AMD trying to answer Nvidia's rack-scale platform story, not just ship a faster accelerator. The caveat is also in the headline: Ethernet-based scale-up could broaden openness, but latency and software maturity will decide whether it competes cleanly with tighter proprietary fabrics. AMD Helios MI455X AI平台曝光，早期系统据称采用UALink-over-Ethernet互连。这个设计显示AMD想回应Nvidia的机架级平台叙事，而不只是推出更快加速器。限制也写在标题里：基于Ethernet的scale-up可能带来更开放生态，但延迟和软件成熟度会决定它能否真正挑战更紧耦合的专有fabric。

Cerebras says it is working with all AI gear makers except Nvidia Cerebras称正与除Nvidia外的AI设备厂合作

Bloomberg via Google News · 8h ago Bloomberg via Google News · 8小时前

Bloomberg reports that Cerebras is working with all AI gear makers except Nvidia. The line is blunt, but strategically coherent: Cerebras is selling itself as the alternative compute layer for vendors and customers that want leverage against Nvidia's full-stack position. The challenge is whether those partnerships translate into deployable systems, software support and supply commitments rather than only anti-incumbent sentiment. Bloomberg报道称，Cerebras正在与除Nvidia外的所有AI设备厂合作。这个说法很直接，但战略上说得通：Cerebras把自己定位为希望制衡Nvidia全栈地位的供应商和客户的替代计算层。挑战在于，这些合作能否转化为可部署系统、软件支持和供应承诺，而不只是反主导厂商情绪。

KT Cloud launches public-sector NPU servers using Rebellions chips KT Cloud推出采用Rebellions芯片的公共部门NPU服务器

Seoul Economic Daily via Google News · 12h ago Seoul Economic Daily via Google News · 12小时前

KT Cloud launched a public-sector NPU server using chips from Rebellions. This is a smaller story than the TSMC and HBM headlines, but it shows sovereign and regional AI infrastructure moving from subsidy language toward specific deployments. For Korean AI-silicon vendors, public-sector procurement can be an early production testbed for software support, utilization and local-stack credibility. KT Cloud推出采用Rebellions芯片的公共部门NPU服务器。这条新闻规模小于TSMC和HBM主线，但它显示主权和区域AI基础设施正在从补贴语言走向具体部署。对韩国AI芯片厂商而言，公共部门采购可以成为软件支持、利用率和本地技术栈可信度的早期量产试验场。

Frore shows a coldplate for Nvidia Vera Rubin-class accelerators Frore展示面向Nvidia Vera Rubin级加速器的冷板

Tom's Hardware · 2h ago Tom's Hardware · 2小时前

Frore showed its LiquidJet Nexus coldplate for Nvidia Vera Rubin and other AI accelerators, claiming a token-generation boost over rival liquid-cooling approaches. The important part is not the exact percentage; it is that cooling vendors are now making performance claims in AI workload language. As accelerator power rises, thermal hardware becomes part of throughput economics rather than a facilities afterthought. Frore展示了面向Nvidia Vera Rubin及其他AI加速器的LiquidJet Nexus冷板，并声称相较其他液冷方案可提升token生成表现。重点不在具体百分比，而在于散热供应商已经开始用AI工作负载语言表达性能。随着加速器功耗上升，热硬件正在变成吞吐经济性的一部分，而不是机房后置配套。

Policy, Materials & Standards 政策、材料与标准

EU proposes Chips Act 2.0 to strengthen its semiconductor ecosystem 欧盟提出Chips Act 2.0强化半导体生态

Digital Watch Observatory via Google News · 1h ago Digital Watch Observatory via Google News · 1小时前

The EU proposed a Chips Act 2.0 aimed at strengthening the semiconductor ecosystem. The policy signal is that Europe is not treating the first Chips Act as a finished industrial plan; it is already adjusting for AI demand, supply-chain resilience and competition for leading-edge investment. Watch whether the second phase adds faster permitting, clearer demand aggregation or more targeted support for packaging and materials. 欧盟提出Chips Act 2.0，目标是强化半导体生态。政策信号在于，欧洲并没有把第一版Chips Act视为已经完成的产业计划，而是在针对AI需求、供应链韧性和先进投资竞争继续调整。后续要看第二阶段是否加入更快审批、更清晰的需求聚合，或更聚焦封装与材料的支持。

China says US export controls disrupt global semiconductor supply chains 中国称美国出口管制扰乱全球半导体供应链

Xinhua via Google News · 21m ago Xinhua via Google News · 21分钟前

Xinhua reports that China criticized US export controls as disruptive to global semiconductor industrial and supply chains. The statement is predictable, but it lands on a day when supply scarcity is already the industry theme. Export-control compliance is now another allocation constraint layered on top of wafer capacity, packaging slots, HBM availability and regional customer access. 新华社报道称，中国批评美国滥用出口管制，扰乱全球半导体产业链和供应链。这个表态并不意外，但它出现的同一天，供应稀缺已经是行业主线。出口管制合规如今是叠加在晶圆产能、封装槽位、HBM可得性和区域客户准入之上的又一层分配约束。

JEDEC releases new SiC guidelines JEDEC发布新的SiC指南

Compound Semiconductor via Google News · 3h ago Compound Semiconductor via Google News · 3小时前

JEDEC released new guidelines for silicon-carbide technology. Standards work rarely moves markets in a single day, but it lowers integration friction for a wide-bandgap supply chain that is still maturing across substrates, devices, modules and qualification. As SiC moves deeper into automotive and power infrastructure, shared guidelines become part of scaling the ecosystem, not just documenting it. JEDEC发布了新的碳化硅技术指南。标准工作通常不会在单日推动市场，但它能降低宽禁带供应链在衬底、器件、模块和认证之间的集成摩擦。随着SiC更深入汽车和电力基础设施，共同指南会成为扩大生态的一部分，而不只是记录生态。