Huawei claims 1.4nm-class chips by 2031 via 'LogicFolding' — no EUV required 华为宣称2031年实现1.4nm级芯片——通过'LogicFolding'架构,无需EUV
Huawei unveiled a chip-design framework it calls 'LogicFolding,' built around what it markets as the 'Tau scaling law' (a replacement for Moore's Law). The pitch: 1.4nm-equivalent transistor density by 2031 with 55% higher density and dramatically lower power, **without** access to EUV lithography. The technical claim is unverified — no working silicon — but the *political* claim is unambiguous: China is asserting it can route around the export-control architecture entirely rather than chase it. Western analysts will spend the next quarter trying to decide whether this is real engineering progress or pre-Computex theater. 华为发布名为'LogicFolding'的芯片设计框架,核心是其所称替代摩尔定律的'Tau Scaling Law'。主张:无需EUV即可在2031年达到1.4nm等效晶体管密度,密度提高55%、功耗显著降低。技术主张尚无实测硅片佐证,但政治主张明确:中国正在表态——不再追赶出口管制架构,而是宣称可以完全绕开。西方分析师未来一个季度的核心争论将是:这是真实的工程突破,还是Computex前的舞台动作。